R&S ESR Series User Manual page 586

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R&S ESR
Table 11-11: Meaning of the bits used in the STATus:QUEStionable:LIMit register
Bit No.
0
1
2
3
4
5
6
7
8 to 14
15
STATus:QUEStionable:LMARgin Register
This register contains information about the observance of limit margins.
You can read out the register with
CONDition?
Table 11-12: Meaning of the bits used in the STATus:QUEStionable:LMARgin register
Bit No.
0
1
2
3
4
5
User Manual 1175.7068.02 ─ 12
Meaning
LIMit 1 FAIL
This bit is set if limit line 1 is violated.
LIMit 2 FAIL
This bit is set if limit line 2 is violated.
LIMit 3 FAIL
This bit is set if limit line 3 is violated.
LIMit 4 FAIL
This bit is set if limit line 4 is violated.
LIMit 5 FAIL
This bit is set if limit line 5 is violated.
LIMit 6 FAIL
This bit is set if limit line 6 is violated.
LIMit 7 FAIL
This bit is set if limit line 7 is violated.
LIMit 8 FAIL
This bit is set if limit line 8 is violated.
Unused
This bit is always 0.
or STATus:QUEStionable:LMARgin<n>[:EVENt]?.
Meaning
LMARgin 1 FAIL
This bit is set if limit margin 1 is violated.
LMARgin 2 FAIL
This bit is set if limit margin 2 is violated.
LMARgin 3 FAIL
This bit is set if limit margin 3 is violated.
LMARgin 4 FAIL
This bit is set if limit margin 4 is violated.
LMARgin 5 FAIL
This bit is set if limit margin 5 is violated.
LMARgin 6 FAIL
This bit is set if limit margin 6 is violated.
STATus:QUEStionable:LMARgin<n>:
Remote Control
Remote Control - Basics
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