R&S ESR Series User Manual page 582

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R&S ESR
The STB can thus be compared with the CONDition part of an SCPI register and
assumes the highest level within the SCPI hierarchy.
The STB is read using the command
The STatus Byte (STB) is linked to the Service Request Enable (SRE) register.
Each bit of the STB is assigned a bit in the SRE. Bit 6 of the SRE is ignored. If a bit is
set in the SRE and the associated bit in the STB changes from 0 to 1, a service
request (SRQ) is generated. The SRE can be set using the command
using the command *SRE?.
Table 11-6: Meaning of the bits used in the status byte
Bit No.
0...1
2
3
4
5
6
7
IST Flag and Parallel Poll Enable Register (PPE)
As with the SRQ, the IST flag combines the entire status information in a single bit. It
can be read by means of a parallel poll (see
command *IST?.
The parallel poll enable register (PPE) determines which bits of the STB contribute to
the IST flag. The bits of the STB are "ANDed" with the corresponding bits of the PPE,
with bit 6 being used as well in contrast to the SRE. The IST flag results from the
"ORing" of all results. The PPE can be set using commands
mand *PRE?.
User Manual 1175.7068.02 ─ 12
Meaning
Not used
Error Queue not empty
The bit is set when an entry is made in the error queue. If this bit is enabled by the SRE, each
entry of the error queue generates a service request. Thus an error can be recognized and
specified in greater detail by polling the error queue. The poll provides an informative error mes-
sage. This procedure is to be recommended since it considerably reduces the problems
involved with remote control.
QUEStionable status register summary bit
The bit is set if an EVENt bit is set in the QUEStionable status register and the associated
ENABle bit is set to 1. A set bit indicates a questionable instrument status, which can be speci-
fied in greater detail by querying the STATus:QUEStionable status register.
MAV bit (message available)
The bit is set if a message is available in the output queue which can be read. This bit can be
used to enable data to be automatically read from the instrument to the controller.
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set
and enabled in the event status enable register. Setting of this bit indicates a serious error which
can be specified in greater detail by polling the event status register.
MSS bit (master status summary bit)
The bit is set if the instrument triggers a service request. This is the case if one of the other bits
of this registers is set together with its mask bit in the service request enable register SRE.
STATus:OPERation status register summary bit
The bit is set if an EVENt bit is set in the OPERation status register and the associated
ENABle bit is set to 1. A set bit indicates that the instrument is just performing an action. The
type of action can be determined by querying the STATus:OPERation status register.
or a serial poll.
*STB?
"Parallel Poll" on page 590) or using the
Remote Control
Remote Control - Basics
and read
*SRE
and read using com-
*PRE
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