32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
PxCFGn
Input
DMUX
Output
MUX
IP
AFIO
OEN
Control
IP
AFIO
PxDOUTn
PxRSTn
PxSETn
GPIO
Figure 20. AFIO / GPIO Control Signal
PxDINn / PxDOUTn (x = A ~ C): Data Input / Data Output
PxRSTn / PxSETn (x = A ~ C): Reset / Set
PxINENn (x = A ~ C): Input Enable
PxODn (x = A ~ C): Open Drain
PxCFGn (x = A ~ C): AFIO Configuration
Table 17. AFIO, GPIO and I/O Pad Control Signal True Table
Type
GPIO Input
(Note)
GPIO Output
(Note)
AFIO Input
AFIO Output
ADC Input
OSC Output
Note: The signals, IEN and OEN, for I/O pads are derived from the GPIO register bits PxINENn and
PxDIRn respectively when the associated pin is configured in the GPIO input / output mode.
Rev. 1.00
IEN
IOPAD
ADC
ADEN
PxDINn
PxINENn
PxDIRn
AFIO
ADEN
OEN
IEN
AFIO
AFIO
AFIO
1
1
1
1
1
1
1
1
0
1
0
1
0
1
1
0
1
1
107 of 486
PUN
PDN
OEN
DS
PxDVn
PxODn
PxPDn
PxPUn
PxDIRn (x = A ~ C): Direction
PxDVn (x = A ~ C): Output Drive
PxPDn / PxPUn (x = A ~ C): Pull Down / Up
GPIO
PxDIRn
PxINENn
ADEN OEN IEN
0
1
1
0 (1 if need)
0
X
X
0 (1 if need)
0
0 (1 if need)
0
0 (1 if need)
PAD
1
1
0
1
0
1 (0)
1
1
0
1
0
1 (0)
0
1
1 (0)
0
1
1 (0)
July 31, 2018
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