Serial Peripheral Interface (Spi); Introduction; Figure 152. Spi Block Diagram - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
20

Serial Peripheral Interface (SPI)

Introduction

The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions
in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and
output lines MISO and MOSI, the clock line SCK, and the slave select line SEL. One SPI device
acts as a master who controls the data flow using the SEL and SCK signals to indicate the start of
the data communication and the data sampling rate. To receive the data bits, the streamlined data
bits which range from 1 bit to 16 bits specified by the DFL field in the SPICR1 register are latched
on a specific clock edge and stored in the data register or in the RX FIFO. Data transmission
is carried in a similar way but with the reverse sequence. The mode fault detection provides a
capability for multi-master applications.
MOSI
MISO
SEL
SCK

Figure 152. SPI Block Diagram

Rev. 1.00
SPIDR
SPI_TXFIFO
Transmit/Receive
Logic
TX Buffer
Shift
Register
RX Buffer
SPI_RXFIFO
420 of 486
Status
SPISR
APB
Bus
SPIFSR
Control
SPICR0
SPICR1
SPIFCR
SPIIER
SPICPR
SPIFTOCR
July 31, 2018