Holtek HT32F50231 User Manual page 436

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[3] WC
[2] RXBNE
[1] TXE
[0] TXBE
Rev. 1.00
Descriptions
Write Collision flag
0: No write collision
1: Write collision has occurred
This bit is set by hardware and cleared by writing 1.
Receive Buffer Not Empty flag
0: RX buffer is empty
1: RX buffer not empty
This bit indicates the RX buffer status in the non-FIFO mode. It is also used to
indicate if the RX FIFO trigger level has been reached in the FIFO mode. This bit will
be cleared when the SPI RX buffer is empty in the non-FIFO mode or if the number
of data contained in RX FIFO is less than the trigger level which is specified by the
RXFTLS field in the SPIFCR register in the SPI FIFO mode.
Transmission Register Empty flag
0: TX buffer or TX shift register is not empty
1: TX buffer and TX shift register both are empty
Transmit Buffer Empty flag
0: TX buffer is not empty
1: TX buffer is empty
In the FIFO mode, this bit, if set, indicates that the number of data contained in TX
FIFO is equal to or less than the trigger level specified by the TXFTLS field in the
SPIFCR register.
436 of 486 July 31, 2018