Figure 12. Power On Reset / Power Down Reset Waveform - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector
The Low Voltage Detector, LVD, can detect whether the supply voltage V
programmable threshold voltage V
When a low voltage on the VDD power pin is detected, the LVDF flag will be active and an
interrupt will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the
LVDCSR register are set. For more details concerning the LVD programmable threshold voltage
V , refer to the electrical characteristics of the corresponding datasheet.
LVD
The Brown Out Detector, BOD, is used to detect if the V
than V . When the BODEN bit in the LVDCSR register is set to 1 and the V
BOD
is lower than V
reset situation and then immediately issue a system reset when the BODRIS bit is cleared to 0 or
issue an interrupt to notify the CPU to execute a power down procedure when the BODRIS bit is
set to 1. For more details concerning the Brown Out Detector voltage V
characteristics of the corresponding datasheet.
High Speed External Oscillator
The High Speed External Oscillator, HSE, is located in the V
oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register
(GCCR). The HSE clock can be used directly as the system clock source.
LSE, LSI and RTC
The Real Time Clock Timer clock source can be derived from either the Low Speed Internal RC
oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power
saving mode by executing WFI / WFE instruction, the MCU needs to setup the compare register
with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup
event. After entering the power saving mode for a certain amount of time, the Compare Match
flag, CMFLAG, will be asserted to wake up the device when the compare match event occurs. The
details of the RTC configuration for wakeup timer will be described in the RTC chapter.
Rev. 1.00
V
DD
V
POR
Hysteresis
POR Delay Time
t
RSTD
RESET
. It is selected by the LVDS bits in the LVDCSR register.
LVD
then the BODF flag is active. The PWRCU will regard this as a power down
BOD
62 of 486
V
PDR
Time
is lower than a
DD
supply voltage is equal to or lower
DD
supply voltage
DD
, refer to the electrical
BOD
power domain. The HSE crystal
DD
July 31, 2018