Interrupts And Status; Register Map; Table 52. Usart Register Map - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Interrupts and Status

The USART can generate interrupts when the following event occurs and corresponding interrupt
enable bits are set:
▄
Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO
is not empty and does not receive a new data package during the specified time-out interval.
▄
Receiver line status interrupts: The interrupts will be generated when the USART receiver
overrun error, parity error, framing error and break events occur.
▄
Transmit FIFO threshold level interrupt: An interrupt will be generated when the data to be
transmitted in the USART Transmit FIFO is less than the specified threshold level.
▄
Transmit complete interrupt: An interrupt will be generated when the Transmit FIFO is empty
and the content of the transmit shift register (TSR) is also completely shifted.
▄
Receive FIFO threshold level interrupt: An interrupt will be generated when the FIFO received
data amount has reached the specified threshold level.

Register Map

The following table shows the USART registers and reset values.

Table 52. USART Register Map

Register
USRDR 0x000
USRCR 0x004
USRFCR 0x008
USRIER 0x00C
USRSIFR 0x010
USRTPR 0x014
IrDACR 0x018
RS485CR 0x01C
SYNCR 0x020
USRDLR 0x024
USRTSTR 0x028
Rev. 1.00
Offset
USART Data Register
USART Control Register
USART FIFO Control Register
USART Interrupt Enable Register
USART Status & Interrupt Flag Register
USART Timing Parameter Register
USART IrDA Control Register
USART RS485 Control Register
USART Synchronous Control Register
USART Divider Latch Register
USART Test Register
450 of 486
Description Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0180
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0010
0x0000_0000
July 31, 2018