Channel 0 Input Configuration Register - Ch0Icfr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Channel 0 Input Configuration Register – CH0ICFR
This register specifies the channel 0 input mode configuration.
Offset: 0x020
Reset value: 0x0000_0000
31
TI0SRC
Type/Reset RW 0
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[31] TI0SRC
[19:18] CH0PSC
[17:16] CH0CCS
Rev. 1.00
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
Reserved
Descriptions
Channel 0 Input Source TI0 Selection
0: The MT_CH0 pin is connected to the channel 0 input TI0
1: The XOR operation output of the MT_CH0, MT_CH1, and MT_CH2 pins are
connected to the channel 0 input TI0
Channel 0 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 0 capture input. Note that the
prescaler is reset once the Channel 0 Capture/Compare Enable bit, CH0E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 0 capture input signal is chosen for each active event
01: Channel 0 Capture input signal is chosen for every 2 events
10: Channel 0 Capture input signal is chosen for every 4 events
11: Channel 0 Capture input signal is chosen for every 8 events
Channel 0 Capture/Compare Selection
00: Channel 0 is configured as an output
01: Channel 0 is configured as an input derived from the TI0 signal
10: Channel 0 is configured as an input derived from the TI1 signal
11: Channel 0 is configured as an input which comes from the TRCED signal
derived from the Trigger Controller
Note: The CH0CCS field can be accessed only when the CH0E bit is cleared to 0.
339 of 486
27 26
Reserved
19 18
CH0PSC
RW 0 RW 0 RW
11 10
Reserved
3 2
RW 0 RW 0 RW
25 24
17 16
CH0CCS
0 RW 0
9 8
1 0
TI0F
0 RW 0
July 31, 2018