Clock Controller; Figure 34. Gptm Clock Source Selection - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Clock Controller

The following describes the Timer Module clock controller which determines the clock source of
the internal prescaler counter.
▄
Internal APB clock f
The default internal clock source is the APB clock f
the slave mode is disabled. When the slave mode selection bits SMSEL in the MDCFR register are
set to 0x4, 0x5 or 0x6, the internal APB clock f
the slave mode controller is enabled by setting SMSEL field in the MDCFR register to an available
value including 0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock sources selected by
the TRSEL field in the TRCFR register and described as follows.
▄
Quadrature Decoder
To select Quadrature Decoder mode the SMSEL field should be set to 0x1, 0x2 or 0x3 in the
MDCFR register. The Quadrature Decoder function uses two input states of the GT_CH0 and
GT_CH1 pins to generate the clock pulse to drive the counter prescaler. The counting direction
bit DIR is modified by hardware automatically at each transition on the input source signal. The
input source signal can be derived from the GT_CH0 pin only, the GT_CH1 pin only or both
GT_CH0 and GT_CH1 pins.
▄
STIED
The counter prescaler can count during each rising edge of the STI signal. This mode can be
selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act
as an event counter. The input event, known as STI here, can be selected by setting the TRSEL
field to an available value except the value of 0x0. When the STI signal is selected as the clock
source, the internal edge detection circuitry will generate a clock pulse during each STI signal
rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
CLKPULSE
(Quadrature Decoder)
f CK_PSC
CLKIN
(Internal APB clock)
STIED
(Trigger events)
TRSEL
SMSEL

Figure 34. GPTM Clock Source Selection

Rev. 1.00
CLKIN
CLKIN
PSCR
CK_CNT
CLK
PSC Prescaler
Reset
Start/Stop
Overflow /
Underflow
189 of 486
used to drive the counter prescaler when
CLKIN
is the counter prescaler driving clock source. If
CRR
CLK
CNTR
Reset
Slave Restart
UEVG bit
mode trigger
Update Event
TM_CNT
July 31, 2018