Holtek HT32F50231 User Manual page 67

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[10] WUP1EN
[9] WUP0IEN
[8] WUP0EN
[7] DMOSON
[3] LDOOFF
Rev. 1.00
Descriptions
External WAKEUP1 Pin Enable
0: Disable WAKEUP1 pin function
1: Enable WAKEUP1 pin function
The Software can set the WUP1EN bit as 1 to enable the WAKEUP1 pin function
before entering the power saving mode. When WUP1EN = 1, a change on the
WAKEUP1 pin wakes up the system from the power saving mode. If the WAKEUP1
pin is active high, this bit will set an input pull down mode. The corresponding
register bits which should be properly setup are the PBPD[9] to 1 in the PBPDR
register, the PBPU[9] to 0 in the PBPUR register and the PBCFG9[3:0] field to 0xF
in the GPBCFGHR register.
Note: Because this bit is located in the V
Power Domain reset. The WAKEUP1 pin signal has to keep a minimum of three 32
kHz clock periods until the activity has been detected for wake up the system.
External WAKEUP0 Pin Interrupt Enable
0: Disable WAKEUP0 pin interrupt function
1: Enable WAKEUP0 pin interrupt function
The software can set the WUP0IEN bit to 1 to assert the WKUP interrupt in the NVIC
unit when both the WUP0EN and WUPF0 bits are set to 1.
External WAKEUP0 Pin Enable
0: Disable WAKEUP0 pin function
1: Enable WAKEUP0 pin function
The Software can set the WUP0EN bit as 1 to enable the WAKEUP0 pin function
before entering the power saving mode. When WUP0EN = 1, a change on the
WAKEUP0 pin wakes up the system from the power saving mode. If the WAKEUP0
pin is active high, this bit will set an input pull down mode. The corresponding
register bits which should be properly setup are the PBPD[12] to 1 in the PBPDR
register, the PBPU[12] to 0 in the PBPUR register and the PBCFG12[3:0] field to
0xF in the GPBCFGHR register.
Note: Because this bit is located in the V
Domain reset. The WAKEUP0 pin signal has to keep a minimum of three 32 kHz
clock periods until the activity has been detected for wake up the system.
DMOS Control
0: DMOS is OFF
1: DMOS is ON
A DMOS is implemented to provide an alternative voltage source for the 1.5 V power
domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control
bit DMOSON is set by software and cleared by software or V
If the DMOSON bit is set to 1, the LDO will automatically be turned off when the
CPU enters the Deep-Sleep mode.
LDO Operating Mode Control
0: The LDO operates in a low current mode when CPU enters the Deep-Sleep mode
(SLEEPDEEP = 1). The V
1: The LDO is turned off when the CPU enters the Deep-Sleep mode (SLEEPDEEP =
1). The V power is not available
DD15
Note: This bit is only available when the DMOSON bit is cleared to 0.
67 of 486
Power Domain and reset by a V
DD15
Power Domain and reset by a V
DD15
power is available
DD15
DD15
Power
DD15
power domain reset.
DD
July 31, 2018