32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
I
2
C Timeout Register – I2CTOUT
This register specifies the I
2
C Timeout counter preload value and clock prescaler ratio.
Offset:
0x028
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
RW
0 RW
7
Type/Reset
RW
0 RW
Bits
Field
[18:16]
PSC
[15:0]
TOUT
Rev. 1.00
30
29
28
22
21
20
Reserved
14
13
12
0 RW
0 RW
6
5
4
0 RW
0 RW
Descriptions
I
2
C Timeout Counter Prescaler Selection
This PSC field is used to specify the I
timeout clock frequency is obtained using the formula.
= f
f
PCLK
I2CTO
2
PSC
PSC = 0 → f
= f
/ 2
I2CTO
PCLK
PSC = 1 → f
= f
/ 2
I2CTO
PCLK
PSC = 2 → f
= f
/ 2
I2CTO
PCLK
...
PSC = 7 → f
= f
/ 2
I2CTO
PCLK
I
2
C Timeout Counter Preload Value
The TOUT field is used to define the counter preloaded value
The counter value is reloaded when any of the following conditions occurs:
1. The RXBF, TXDE, RXDNE, RXNACK, GCS or ADRS flag in the I2CSR register
is asserted.
2. The I
2
C master module sends a START signal.
3. The I
2
C slave module detects a START signal.
The counter stops counting when any of the following conditions occurs:
1. The I
2
C slave device is not addressed.
2. The I
C master module sends a STOP signal.
2
3. The I
2
C slave module detects a STOP signal.
4. The ARBLOS or BUSERR flag in the I2CSR register is asserted.
419 of 486
27
26
Reserved
19
18
RW
0 RW
11
10
TOUT
0 RW
0 RW
0 RW
3
2
TOUT
0 RW
0 RW
0 RW
2
C timeout counter clock frequency, f
0
= f
PCLK
1
= f
/ 2
PCLK
2
= f
/ 4
PCLK
7
= f
/ 128
PCLK
25
24
17
16
PSC
0 RW
0
9
8
0 RW
0
1
0
0 RW
0
. The
I2CTO
July 31, 2018
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