Register Map; Table 11. Enter / Exit Power Saving Modes; Table 12. Power Status After System Reset; Table 13. Pwrcu Register Map - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Table 11. Enter / Exit Power Saving Modes

Mode
CPU
Instruction SLEEPDEEP
Sleep
WFI or WFE
(Takes effect)
Deep-Sleep1
Deep-Sleep2
Notes: 1. Wakeup event means EXTI line in event mode, RTC, LVD and WAKEUP pins
2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode,
the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system
can be woken up by an LVD event and then the LDO regulator can be turned on when system is woken
up from the Deep-Sleep2 mode.
Deep-Sleep Mode
To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute
the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including high speed oscillator,
known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO into low current
mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.5 V power. Once the
PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode-Exiting table, the
LDO will then operate in normal mode and the high speed oscillator will be enabled. Finally, the
CPU will return to Run mode to handle the wakeup interrupt if required. A Low Voltage Detection
also can be regarded as a wakeup event if the corresponding wakeup control bit LVDEWEN in the
LVDCSR register is enabled. The last wakeup event is a transition on the external WAKEUP pin
sent to the PWRCU to resume from Deep-Sleep mode. During the Deep-Sleep mode, retaining the
register and memory contents will shorten the wakeup latency.

Table 12. Power Status After System Reset

PORF PORSTF
1 1
0 1

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit
are located in the V

Table 13. PWRCU Register Map

Register Offset
PWRSR 0x100
PWRCR 0x104
LVDCSR 0x110
Rev. 1.00
Mode Entry
CPU
LDOOFF DMOSON
0 X X
1 0 0
1 X 1
Power-up for the first time after the V
Power on reset when V is applied for the first time or executing software reset
DD
command on the V domain.
DD
Restart from unexpected loss of the 1.5 V power or other reset (nRST, WDT, ...)
power domain.
DD15
Description
Power Control Status Register
Power Control Register
Low Voltage / Brown Out Detect Control and Status Register 0x0000_0000
64 of 486
Mode Exit
WFI: Any interrupt
WFE:
Any wakeup event (1) or
Any interrupt (NVIC on) or
Any interrupt with SEVONPEND = 1 (NVIC off)
Any EXTI in event mode or
RTC wakeup or LVD wakeup (2) or
WAKEUP pins
Any EXTI in event mode or
RTC wakeup or LVD wakeup (2)
WAKEUP pins
Description
power domain is reset:
DD
or
Reset Value
0x0000_0010
0x0000_0000
July 31, 2018