I 2 C Address Mask Register - I2Caddmr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
I 2 C Address Mask Register – I2CADDMR
This register specifies which bit of the I
received address frame.
Offset: 0x020
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[9:0] ADDMR
Rev. 1.00
2 C address is masked and not compared with corresponding bit of the
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
0 RW 0 RW
Descriptions
Address Mask Control Bit
The ADDMR[i] is used to specify whether the i
register is masked and is compared with the received address frame or not on the
I 2 C bus. The register is only used for the I
0: i bit of the ADDR is compared with the address frame on the I
th
1: i th bit of the ADDR is masked and not compared with the address frame on the
I 2 C bus
417 of 486
27 26
Reserved
19 18
Reserved
11 10
RW
3 2
ADDMR
0 RW 0 RW 0 RW
th bit of the ADDR in the I2CADDR
2 C slave mode only.
25 24
17 16
9 8
ADDMR
0 RW 0
1 0
0 RW 0
C bus
2
July 31, 2018