Holtek HT32F50231 User Manual page 97

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[13] DBI2C1
[12] DBI2C0
[11] DBSPI1
[10] DBSPI0
[8] DBUSR
[6] DBGPTM
[4] DBMCTM
[3] DBWDT
[1] DBDSLP1
[0] DBSLP
Rev. 1.00
Descriptions
I 2 C1 Debug Mode Enable
0: Same behavior as in normal mode
1: I 2 C1 timeout is frozen when the core is halted
Set and reset by software.
I 2 C0 Debug Mode Enable
0: Same behavior as in normal mode
1: I 2 C0 timeout is frozen when the core is halted
Set and reset by software.
SPI1 Debug Mode Enable
0: Same behavior as in normal mode
1: SPI1 FIFO timeout is frozen when the core is halted
Set and reset by software.
SPI0 Debug Mode Enable
0: Same behavior as in normal mode
1: SPI0 FIFO timeout is frozen when the core is halted
Set and reset by software.
USART Debug Mode Enable
0: Same behavior as in normal mode
1: USART timeout is frozen when the core is halted
Set and reset by software.
GPTM Debug Mode Enable
0: GPTM counter continues to count even if the core is halted
1: GPTM counter is stopped when the core is halted
Set and reset by software.
MCTM Debug Mode Enable
0: MCTM counter continues even if the core is halted
1: MCTM counter is stopped when the core is halted
Set and reset by software.
Watchdog Timer Debug Mode Enable
0: Watchdog Timer counter continues to count even if the core is halted
1: Watchdog Timer counter is stopped when the core is halted
Set and reset by software.
Debug Deep-Sleep1
0: LDO = Low power mode, FCLK = Off and HCLK = Off in Deep-Sleep1 mode
1: LDO = On, FCLK = On and HCLK = On in Deep-Sleep1 mode
Set and reset by software.
Debug Sleep Mode
0: LDO = On, FCLK = On and HCLK = Off in Sleep mode
1: LDO = On, FCLK = On and HCLK = On in Sleep mode
Set and reset by software.
97 of 486 July 31, 2018