Adc Interrupt Clear Register - Adciclr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
ADC Interrupt Clear Register – ADCICLR
This register provides the clear bits used to clear the interrupt raw and interrupt status of the ADC. These bits are
set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.
Offset: 0x08C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[24] ADICLRO
[17] ADICLRU
[16] ADICLRL
[2] ADICLRC
[1] ADICLRG
[0] ADICLRS
Rev. 1.00
30 29 28
Reserved
22 21 20
Reserved
14 13 12
6 5 4
Reserved
Descriptions
ADC Data Register Overwrite Interrupt Status Clear Bit
0: No effect
1: Clear ADISRO and ADIRAWO bits
ADC Watchdog Upper Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADISRU and ADIRAWU bits
ADC Watchdog Lower Threshold Interrupt Status Clear Bit
0: No effect
1: Clear ADISRL and ADIRAWL bits
ADC Cycle EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADISRC and ADIRAWC bits
ADC Subgroup EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADISRG and ADIRAWG bits
ADC Single EOC Interrupt Status Clear Bit
0: No effect
1: Clear ADISRS and ADIRAWS bits
184 of 486
27 26
19 18
ADICLRU
WO
11 10
Reserved
3 2
ADICLRC ADICLRG
WO 0 WO
25 24
ADICLRO
WO 0
17 16
ADICLRL
0 WO 0
9 8
1 0
ADICLRS
0 WO 0
July 31, 2018