32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
4
Flash Memory Controller (FMC)
Introduction
The Flash Memory Controller, FMC, provides functions of flash operation and pre-fetch buffer
for the embedded on-chip Flash memory. Figure below shows the block diagram of FMC which
includes programming interface, control register, pre-fetch buffer and access interface. Since the
access speed of Flash memory is slower than the CPU, a wide access interface with pre-fetch buffer
is provided to the Flash memory in order to reduce the CPU wait state, which will cause instruction
gaps. The functions of word programming / page erase are also provided for instruction / data
storage of Flash memory.
AHB
Peripheral
Bus
System Bus
Figure 5. Flash Memory Controller Block Diagram
Features
▄
Up to 64 KB of on-chip Flash memory for storing instruction / data and option bytes
●
64 KB (instruction / data + Option Byte)
●
32 KB (instruction / data + Option Byte)
▄
Page size of 1 KB, totally up to 64 pages depending on the main Flash size
▄
Wide access interface with pre-fetch buffer to reduce instruction gaps
▄
Page erase and mass erase capability
▄
32-bit word programming
▄
Interrupt capability when ready or error occurs
▄
Flash read protection to prevent illegal code / data access
▄
Page erase / program protection to prevent unexpected operation
Rev. 1.00
Flash Memory Controller
Control Register
Pre-fetch Buffer
34 of 486
Information
Wait State
Control
Addressing
Main Flash
Data
Memory
Programming
Control
Flash
Block
July 31, 2018
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