1.5 V Power Domain; Operation Modes; Table 10. Operation Mode Definitions - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

1.5 V Power Domain

The main functions that include high speed internal oscillator, HSI, MCU core logic, AHB / APB
peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered
up, the POR will generate a reset sequence on 1.5 V power domain. Subsequently, to enter the
expected power saving mode, the associated control bits including the LDOOFF, DMOSON and
LDOLCM bits must be configured. Then, once a WFI or WFE instruction is executed, the device
will enter an expected power saving mode which will be discussed in the following section.
High Speed Internal Oscillator
The High Speed Internal Oscillator, HSI, is located in the V
the Deep-Sleep mode, the HSI clock will be configured as the system clock for a certain period by
setting the PSRCEN bit to 1. This bit is located in the Global Clock Control Register, GCCR, in the
Clock Control Unit, CKCU. The system clock will not be switched back to the original clock source
used before entering the Deep-Sleep mode until the original clock source stabilizes.

Operation Modes

Run Mode
In the Run mode, the system operates with full functions and all power domains are active. There
are two ways to reduce the power consumption in this mode. The first is to slow down the system
clock by setting the AHBPRE field in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application
requirement. Reducing the system clock speed before entering the sleep mode will also help to
minimize power consumption.
Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 10. Operation Mode Definitions

Mode Name
Run
Sleep
Deep-Sleep1 ~ 2
Sleep Mode
By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash
clock or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to
access the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN
and SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep
mode, it is only CPU executes a WFI or WFE instruction and lets the SLEEPDEEP signal to 0. The
system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.
Rev. 1.00
After system reset, CPU fetches instructions to execute.
1. CPU clock will be stopped.
2. Peripherals, Flash and SRAM clocks can be stopped by setting.
1. Stop all clocks in the 1.5 V power domain.
2. Disable HSI, HSE.
3. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.
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power domain. When exiting from
DD15
Hardware Action
July 31, 2018