Rtc Control Register - Rtccr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
RTC Control Register – RTCCR
This register specifies a range of RTC circuitry control bits.
Offset: 0x008
Reset value: 0x0000_0F00 (Reset by V
31
Type/Reset
23
Reserved
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[20] ROLF
[19] ROAP
[18] ROWM
[17] ROES
[16] ROEN
Rev. 1.00
Power Domain reset only)
DD15
30 29 28
22 21 20
ROLF
RC
14 13 12
Reserved
6 5 4
LSESM CMPCLR
RW 0 RW
Descriptions
RTCOUT Level Mode Flag
0: RTCOUT Output is inactive
1: RTCOUT Output is holding as active level
Set by hardware when in the level mode (ROWM = 1) and an RTCOUT output event
occurred. Cleared by software reading this flag. The RTCOUT signal will return to
the inactive level after software has read this bit.
RTCOUT Output Active Polarity
0: Active level is high
1: Active level is low
RTCOUT Output Waveform Mode
0: Pulse mode
The output pulse duration is one RTC clock (CK_RTC) period.
1: Level mode
The RTCOUT signal will remain at an active level until the ROLF bit is cleared
by software reading the ROLF bit.
RTCOUT Output Event Selection
0: RTC compare match is selected
1: RTC second clock (CK_SECOND) event is selected
The ROES bit can be used to select whether the RTCOUT signal is output on the
RTCOUT pin when an RTC compare match event or the RTC second clock (CK_
SECOND) event occurs.
RTCOUT Output Pin Enable
0: Disable RTCOUT output pin
1: Enable RTCOUT output pin
When the ROEN bit is set to 1, the RTCOUT signal will be at an active level once
a RTC compare match or the RTC second clock (CK_SECOND) event occurs. The
active polarity and output waveform mode can be configured by the ROAP and
ROWM bits respectively. When the ROEN bit is cleared to 0, the RTCOUT pin will
be in a floating state.
378 of 486
27 26
Reserved
19 18
ROAP ROWM
0 RW 0 RW 0 RW
11 10
RW 1 RW 1 RW
3 2
LSEEN Reserved
0 RW 0 RW
25 24
17 16
ROES ROEN
0 RW 0
9 8
RPRE
1 RW 1
1 0
RTCSRC RTCEN
0 RW 0
July 31, 2018