Usart Status & Interrupt Flag Register - Usrsifr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
USART Status & Interrupt Flag Register – USRSIFR
This register contains the corresponding USART status.
Offset: 0x010
Reset value: 0x0000_0180
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
TXDE
Type/Reset RO 1 WC
Bits Field
[11] CTSS
[10] CTSC
[9] RSADD
[8] TXC
[7] TXDE
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5
RXTOF RXDR BII
0 RO 0 WC
Descriptions
CTS Clear-To-Send Status
0: CTS pin is inactive
1: CTS pin is active and kept at a logic low state
CTS Status Change Flag
This bit will be set whenever the CTS input pin status is changed and an Interrupt will
be generated if the CTSIE = 1 in the USRIER register. Writing 1 to this bit clears the
flag.
RS485 Address Detection
0: Address is not detected
1: Address is detected
This bit will be set to 1 when the receiver detects the address. An interrupt will be
generated if RSADDIE = 1 in the USRIER register. Writing 1 to this bit clears the flag.
Note: This bit is only used in the RS485 mode by setting the MODE field in the
USRCR register.
Transmit Complete
0: Either transmit FIFO (TX FIFO) or transmit shift register (TSR) is not empty
1: Both the TX FIFO and TSR register are empty
An interrupt will be generated if TXCIE = 1 in the USRIER register. This bit is cleared
by a write to the USRDR register with new data.
Transmit Data FIFO Empty
0: TX FIFO level is higher than threshold
1: TX FIFO level is less than threshold
The TXDE bit will be set when transmit FIFO level is less than the transmit FIFO
threshold level setting which is set by the TXTL field in the USRFCR register. This
bit will be cleared when the new data is written into the USRDR register and the TX
FIFO level is higher than threshold setting.
457 of 486
27 26
Reserved
19 18
Reserved
11 10
CTSS CTSC
RO 0 WC
4 3 2
FEI PEI
0 WC 0 WC
25 24
17 16
9 8
RSADD TXC
0 WC 0 RO 1
1 0
OEI RXDNE
0 WC 0 RO 0
July 31, 2018