32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Flash Page Erase / Program Protection Status Register – PPSR
This register indicates the status of Flash page erase / program protection.
Offset:
0x020 (0) ~ 0x02C (3)
Reset value: 0xXXXX_XXXX
31
Type/Reset
RO
X RO
23
Type/Reset
RO
X RO
15
Type/Reset
RO
X RO
7
Type/Reset
RO
X RO
Bits
Field
[127:0]
PPSBn
Rev. 1.00
30
29
28
X RO
X RO
22
21
20
X RO
X RO
14
13
12
X RO
X RO
6
5
4
X RO
X RO
Descriptions
Page Erase / Program Protection Status Bits (n = 0 ~ 127)
PPSB[n] = OB_PP[n]
0: The corresponding page is protected
1: The corresponding page is not protected
The content of this register is not dynamically updated and will only be reloaded
from the Option Byte when any kind of reset occurs. The erase or program function
of specific pages is not allowed when the corresponding bits of the PPSR registers
are reset. The reset value of PPSR [127:0] is determined by the Option Byte OB_
PP [127:0]. Since the maximum page number of the main flash is various and
dependent on the chip specification. Therefore, the every page erase / program
protection status bit may protect one or two pages and dependent on the chip
specification. The other remained bits of OB_PP and PPSR registers are reserved.
52 of 486
27
26
PPSBn
X RO
X RO
X RO
19
18
PPSBn
X RO
X RO
X RO
11
10
PPSBn
X RO
X RO
X RO
3
2
PPSBn
X RO
X RO
X RO
25
24
X RO
X
17
16
X RO
X
9
8
X RO
X
1
0
X RO
X
July 31, 2018
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