Channel 1 Input Configuration Register - Ch1Icfr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[3:0] TI0F
Channel 1 Input Configuration Register – CH1ICFR
This register specifies the channel 1 input mode configuration.
Offset: 0x024
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[19:18] CH1PSC
Rev. 1.00
Descriptions
Channel 0 Input Source TI0 Filter Setting
These bits define the frequency divided ratio used to sample the TI0 signal. The
Digital filter in the MCTM is an N-event counter where N is defined as how many
valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
0001: f = f , N = 2
SAMPLING CLKIN
0010: f = f , N = 4
SAMPLING CLKIN
0011: f = f , N = 8
SAMPLING CLKIN
0100: f = f / 2, N = 6
SAMPLING DTS
0101: f = f / 2, N = 8
SAMPLING DTS
0110: f = f / 4, N = 6
SAMPLING DTS
0111: f = f / 4, N = 8
SAMPLING DTS
1000: f = f / 8, N = 6
SAMPLING DTS
1001: f = f / 8, N = 8
SAMPLING DTS
1010: f = f / 16, N = 5
SAMPLING DTS
1011: f = f / 16, N = 6
SAMPLING DTS
1100: f = f / 16, N = 8
SAMPLING DTS
1101: f = f / 32, N = 5
SAMPLING DTS
1110: f = f / 32, N = 6
SAMPLING DTS
1111: f = f / 32, N = 8
SAMPLING DTS
30 29 28
22 21 20
Reserved
14 13 12
6 5 4
Reserved
Descriptions
Channel 1 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 1 capture input. Note that the
prescaler is reset once the Channel 1 Capture/Compare Enable bit, CH1E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 1 capture input signal is chosen for each active event
01: Channel 1 Capture input signal is chosen for every 2 events
10: Channel 1 Capture input signal is chosen for every 4 events
11: Channel 1 Capture input signal is chosen for every 8 events
340 of 486
SYSTEM
27 26
Reserved
19 18
CH1PSC
RW 0 RW 0 RW
11 10
Reserved
3 2
RW 0 RW 0 RW
25 24
17 16
CH1CCS
0 RW 0
9 8
1 0
TI1F
0 RW 0
July 31, 2018