Adc Watchdog Control Register - Adcwcr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[11:8] ADEXTIS
[0] ADSC
ADC Watchdog Control Register – ADCWCR
This register provides the control bits and status of the ADC watchdog function.
Offset: 0x078
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[27:24] ADUCH
Rev. 1.00
Descriptions
EXTI Trigger Source Selection of ADC Conversion
0x00: EXTI line 0
0x01: EXTI line 1
...
0x0F: EXTI line 15
Note that the EXTI line active edge to start an A/D conversion is determined in the
External Interrupt / Event Control Unit, EXTI.
ADC Conversion Software Trigger Bit
0: Reset
1: Start conversion immediately
This bit is set by software to start a conversion manually and then cleared by
hardware automatically after conversion is started.
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Upper Threshold Channel Status
0000: ADC_IN0 is higher than the upper threshold
0001: ADC_IN1 is higher than the upper threshold
...
1011: ADC_IN11 is higher than the upper threshold
Others: Reserved
If both the ADWUE and ADWALL status bits are set to 1 by the watchdog monitor
function, this status field value should first be stored in the user-defined memory
location in the corresponding ISR. Otherwise, the ADUCH field will be changed if
another input channel converted data is higher than the upper threshold.
178 of 486
27 26
ADUCH
RO 0 RO 0 RO
19 18
ADLCH
RO 0 RO 0 RO
11 10
ADWCH
RW 0 RW 0 RW
3 2
ADWALL ADWUE
RW 0 RW
25 24
0 RO 0
17 16
0 RO 0
9 8
0 RW 0
1 0
ADWLE
0 RW 0
July 31, 2018