Timer Counter Register - Ctr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Timer Counter Register – CTR
This register specifies the timer enable bit (TME) and CRR buffer enable bit (CRBE).
Offset: 0x010
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[1] CRBE
[0] TME
Rev. 1.00
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Counter Reload register Buffer Enable
0: Counter reload register can be updated immediately
1: Counter reload register can not be updated until the update event occurs
Timer Enable bit
0: PWM off
1: PWM on
When the TME bit is cleared to 0, the counter is stopped and the PWM consumes no
power in any operation mode except for the single pulse mode and the slave trigger
mode. In these two modes the TME bit can automatically be set to 1 by hardware
which permits all the PWM registers to function normally.
272 of 486
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
CRBE
RW
25 24
17 16
9 8
1 0
TME
0 RW 0
July 31, 2018