Holtek HT32F50231 User Manual
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Holtek HT32F50231 User Manual

32-bit microcontroller with arm cortex-m0+
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Holtek 32-Bit Microcontroller with Arm
®
Cortex
®
-M0+
HT32F50231/HT32F50241
User Manual
Revision: V1.00
Date: July 31, 2018

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Summary of Contents for Holtek HT32F50231

  • Page 1 Holtek 32-Bit Microcontroller with Arm ® Cortex ® -M0+ HT32F50231/HT32F50241 User Manual Revision: V1.00 Date: July 31, 2018...

  • Page 2: Table Of Contents

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table of Contents 1 Introduction ......................21 Overview ..........................21 Features ..........................22 Device Information ....................... 25 Block Diagram ........................26 2 Document Conventions ..................27 3 System Architecture ..................... 28 ®...
  • Page 3 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Manufacturer and Device ID Register – MDID ..............55 Flash Page Number Status Register – PNSR ................56 Flash Page Size Status Register – PSSR ..................57 Device ID Register – DIDR ......................58 Custom ID Register n –...
  • Page 4 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Peripheral Clock Selection Register 0 – APBPCSR0 ............. 90 APB Peripheral Clock Selection Register 1 – APBPCSR1 ............. 92 HSI Control Register – HSICR ......................93 HSI Auto Trimming Counter Register – HSIATCR ................94 APB Peripheral Clock Selection Register 2 –...
  • Page 5 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Pull-Down Selection Register – PBPDR ................122 Port B Open-Drain Selection Register – PBODR ................. 123 Port B Output Drive Current Selection Register – PBDRVR ............124 Port B Lock Register – PBLOCKR ....................125 Port B Data Input Register –...
  • Page 6 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 11 External Interrupt / Event Controller (EXTI) ............ 149 Introduction ........................149 Features ..........................149 Function Descriptions ......................150 Wakeup Event Management......................150 External Interrupt / Event Line Mapping ..................151 Interrupt and Debounce ........................ 151 Register Map ........................
  • Page 7 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Interrupt Status Register – ADCISR ..................183 ADC Interrupt Clear Register – ADCICLR ..................184 13 General-Purpose Timer (GPTM) ..............185 Introduction ........................185 Features ..........................185 Functional Descriptions ..................... 186 Counter Mode ..........................
  • Page 8 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Capture / Compare Register – CH1CCR ..............242 Channel 2 Capture / Compare Register – CH2CCR ..............243 Channel 3 Capture / Compare Register – CH3CCR ..............244 Channel 0 Asymmetric Compare Register – CH0ACR ..............245 Channel 1 Asymmetric Compare Register –...
  • Page 9 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Compare Register – CH3CR ..................289 Channel 0 Asymmetric Compare Register – CH0ACR ..............290 Channel 1 Asymmetric Compare Register – CH1ACR ..............290 Channel 2 Asymmetric Compare Register – CH2ACR ..............291 Channel 3 Asymmetric Compare Register –...
  • Page 10 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Input Configuration Register – CH1ICFR ..............340 Channel 2 Input Configuration Register – CH2ICFR ..............342 Channel 3 Input Configuration Register – CH3ICFR ..............343 Channel 0 Output Configuration Register – CH0OCFR ............... 345 Channel 1 Output Configuration Register –...
  • Page 11 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 18 Watchdog Timer (WDT) ..................382 Introduction ........................382 Features ..........................382 Functional Description ....................... 383 Register Map ........................385 Register Descriptions ......................385 Watchdog Timer Control Register – WDTCR ................385 Watchdog Timer Mode Register 0 –...
  • Page 12 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 20 Serial Peripheral Interface (SPI) ..............420 Introduction ........................420 Features ..........................421 Function Descriptions ......................421 Master Mode ..........................421 Slave Mode ........................... 421 SPI Serial Frame Format ......................422 Status Flags ..........................426 Register Map ........................
  • Page 13 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 22 Universal Asynchronous Receiver Transmitter (UART) ........ 465 Introduction ........................465 Features ..........................466 Function Descriptions ......................466 Serial Data Format ........................466 Baud Rate Generation ........................467 Interrupts and Status ........................468 Register Map ........................
  • Page 14 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 List of Tables Table 1. Features and Peripheral List ..................... 25 Table 2. Document Conventions ......................27 Table 3. Register Map ..........................32 Table 4. Flash Memory and Option Byte ....................36 Table 5.
  • Page 15 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 40. RTCOUT Output Mode and Active Level Setting ..............375 Table 41. RTC Register Map......................... 376 Table 42. Watchdog Timer Register Map ....................385 Table 43. Conditions of Holding SCL line ....................404 Table 44.
  • Page 16 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 List of Figures Figure 1. Block Diagram ......................... 26 Figure 2. Cortex -M0+ Block Diagram ....................29 ® Figure 3. Bus Architecture ........................30 Figure 4. Memory Map ..........................31 Figure 5. Flash Memory Controller Block Diagram ................. 34 Figure 6.
  • Page 17 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 40. Master GPTMn and Slave GPTMm / MCTMm Connection ..........193 Figure 41. MTO Selection ........................193 Figure 42. Capture / Compare Block Diagram ..................194 Figure 43. Input Capture Mode ......................195 Figure 44.
  • Page 18 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 81. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ..259 Figure 82. Update Event Setting Diagram .................... 260 Figure 83. Single Pulse Mode ....................... 261 Figure 84. Immediate Active Mode Minimum Delay ................262 Figure 85.
  • Page 19 Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 121. Channel 3 Output with a Break Event Occurrence ............317 Figure 122. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence......318 Figure 123. Channel 0 ~2 Only One Output Enabled when Break Event Occurs ........ 319 Figure 124.
  • Page 20 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 162. USART Block Diagram ...................... 440 Figure 163. USART Serial Data Format ....................442 Figure 164. USART Clock CK_USART and Data Frame Timing ............442 Figure 165. Hardware Flow Control between 2 USARTs ..............443 Figure 166.

  • Page 21: Introduction

    Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The devices operate at a frequency of up to 20 MHz for HT32F50231/50241 to obtain maximum efficiency. It provides up to 64 KB of embedded Flash memory for code / data storage and 8 KB of embedded SRAM memory for system operation and application program usage.

  • Page 22: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Core ● 32-bit Arm ® Cortex ® -M0+ processor core ● Up to 20 MHz operating frequency ● Single-cycle multiplication ● Integrated Nested Vectored Interrupt Controller (NVIC) ● 24-bit SysTick timer ▄...
  • Page 23 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ▄ I/O ports – GPIO ● Up to 40 GPIOs ● Port A, B, C are mapped as 16 external interrupts – EXTI ● Almost I/O pins are configurable output driving current ▄...
  • Page 24 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ▄ Inter-integrated Circuit – I ● Supports both master and slave modes with a frequency of up to 1 MHz ● Provides an arbitration function and clock synchronization ● Supports 7-bit and 10-bit addressing modes and general call addressing ●...

  • Page 25: Device Information

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ▄ Package and Operation Temperature ● 24/28-pin SSOP, 28-pin SOP, 24/33-pin QFN and 44/48-pin LQFP package types ● Operation temperature range: -40 °C to 85 °C Device Information Table 1. Features and Peripheral List...

  • Page 26: Block Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Block Diagram SWCLK PA ~ PB[15:0], PC[7:0] BOOT SWDIO Powered by V DD15 /PDR Flash Memory Flash SW-DP Interface Memory GPIO XTALIN XTALOUT Cortex -M0+ ® 4 ~ 20 MHz Processor CKCU/RSTCU...

  • Page 27: Document Conventions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Document Conventions Unless otherwise specified, this document uses the conventions which showed as follows. Table 2. Document Conventions Notation Example Description The number string with a 0x prefix indicates a hexadecimal 0x5a05 number.

  • Page 28: System Architecture

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 System Architecture The system architecture of devices that includes the Arm Cortex -M0+ processor, bus architecture ® ® and memory organization will be described in the following sections. The Cortex ® -M0+ is a next generation processor core which offers many new features.

  • Page 29: Bus Architecture

    Figure 2. Cortex ® -M0+ Block Diagram Bus Architecture The HT32F50231/50241 series devices consist of one master and four slaves in the bus architecture. The Cortex ® -M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the slaves.

  • Page 30: Memory Organization

    Cortex -M0+ ® ® ® ® Technical Reference Manual for more information. The following figure shows the memory map of HT32F50231/50241 series of devices, including Code, SRAM, peripheral and other pre-defined regions. Rev. 1.00 30 of 486 July 31, 2018...

  • Page 31: Memory Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Memory Map 0xFFFF_FFFF 0x400F_FFFF Reserved Reserved 0x400C_C000 0xE010_0000 0x400C_A000 Reserved Private peripheral bus 0x400B_6000 0xE000_0000 GPIO A ～ C 0x400B_0000 Reserved 0x4008_C000 0x4008_A000 CKCU & RSTCU 0x4008_8000 Reserved 0x4008_2000 0x4008_0000 Reserved Reserved...

  • Page 32: Table 3. Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 3. Register Map Start Address End Address Peripheral 0x4000_0000 0x4000_0FFF USART 0x4000_1000 0x4000_1FFF UART0 0x4000_2000 0x4000_3FFF Reserved 0x4000_4000 0x4000_4FFF SPI0 0x4000_5000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF 0x4001_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_2FFF AFIO...

  • Page 33: Embedded Flash Memory

    HT32F50231/HT32F50241 Embedded Flash Memory The HT32F50231/50241 series provide up to 64 KB on-chip Flash memory which is located at address 0x0000_0000. It supports byte, half-word and word access operations. Note that the Flash memory only supports read operations for the bus access. Any write operations to the Flash memory will cause a bus fault exception.

  • Page 34: Flash Memory Controller (Fmc)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Memory Controller (FMC) Introduction The Flash Memory Controller, FMC, provides functions of flash operation and pre-fetch buffer for the embedded on-chip Flash memory. Figure below shows the block diagram of FMC which includes programming interface, control register, pre-fetch buffer and access interface.

  • Page 35: Functional Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Descriptions Flash Memory Map The following figure is the Flash memory map of the system. The address ranges from 0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is mapped to Boot Loader Block (2 KB).

  • Page 36: Flash Memory Architecture

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Memory Architecture The Flash memory consists of up to 64 KB main Flash with 1 KB per page and 2 KB Information Block for Boot Loader. The main Flash memory contains totally 64 pages (or 32 pages for 32 KB device) which can be erased individually.

  • Page 37: Booting Configuration

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Booting Configuration The system provides two kinds of booting mode which can be selected through the BOOT pin. The value of BOOT pin is sampled during the power-on reset or system reset. Once the logic value is decided, the first 4 words of vector will be remapped to the corresponding source according to the booting mode.

  • Page 38: Page Erase

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Page Erase The FMC provides a page erase function which is used to reset partial content of Flash memory. Any page can be erased independently without affecting others. The following steps show the access sequence of the register for page erase.

  • Page 39: Mass Erase

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Mass Erase The FMC provides a mass erase function which is used for resetting all the main Flash memory content. The following steps show the register access sequence for mass erase operation. ▄...

  • Page 40: Word Programming

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Word Programming The FMC provides a 32 bits word programming function which is used for modifying the Flash memory content. The following steps show the sequence of register access for word programming. ▄...

  • Page 41: Option Byte Description

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Option Byte Description The Option Byte can be treated as an independent Flash memory of which base address is 0x1FF0_0000. The following table shows the function description and Option Byte memory map. Table 6. Option Byte Memory Map...

  • Page 42: Page Erase / Program Protection

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Page Erase / Program Protection FMC provides functions of page erase / program protection to prevent unexpected operation of Flash memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word programming (CMD [3:0] = 0x4) command will not be accepted by FMC on the protected pages.

  • Page 43: Security Protection

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Security Protection FMC provides a Security protection function to prevent illegal code / data access of the Flash memory. This function is useful for protecting the software / firmware from illegal users. The function is activated by setting the Option Byte OB_CP [0] bit. Once the function has been enabled, all the main Flash data access through ICP / Debug mode, programming and page erase will not be allowed except the user’s application.

  • Page 44: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the FMC registers and reset values. Table 9. FMC Register Map Register Offset Description Reset Value TADR 0x000 Flash Target Address Register 0x0000_0000 WRDR 0x004 Flash Write Data Register...

  • Page 45: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions Flash Target Address Register – TADR This register specifies the target address of the page erase and word programming operation. Offset: 0x000 Reset value: 0x0000_0000 TADB Type/Reset 0 RW 0 RW...

  • Page 46: Flash Write Data Register - Wrdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Write Data Register – WRDR This register specifies the data to be written for programming operation. Offset: 0x004 Reset value: 0x0000_0000 WRDB Type/Reset 0 RW 0 RW 0 RW 0 RW...

  • Page 47: Flash Operation Command Register - Ocmr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Operation Command Register – OCMR This register is used to specify the Flash operation commands that include word programming, page erase and mass erase. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 48: Flash Operation Control Register - Opcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Operation Control Register – OPCR This register is used for controlling the command commitment and checking the status of the FMC operations. Offset: 0x010 Reset value: 0x0000_000C Reserved Type/Reset Reserved Type/Reset...

  • Page 49: Flash Operation Interrupt Enable Register - Oier

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Operation Interrupt Enable Register – OIER This register is used to enable or disable interrupt function of FMC. The FMC will generate interrupts when the corresponding interrupt enable bit is set and the interrupt condition occurs.

  • Page 50: Flash Operation Interrupt And Status Register - Oisr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Operation Interrupt and Status Register – OISR This register indicates the status of the FMC interrupt to check if an operation has been finished or an error occurs. The status bits, bit [4:0], if set high, are available to trigger the interrupt when the corresponding enable bits in the OIER register are set high.
  • Page 51 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions OBEF Option Byte Check Sum Error Flag 0: Check sum of Option Byte is correct 1: Check sum of Option Byte is incorrect This bit will be set high when the Option Byte checksum is incorrect. The OBE interrupt will occur if the OBEIEN bit in the OIER register is set.

  • Page 52: Flash Page Erase / Program Protection Status Register - Ppsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Page Erase / Program Protection Status Register – PPSR This register indicates the status of Flash page erase / program protection. Offset: 0x020 (0) ~ 0x02C (3) Reset value: 0xXXXX_XXXX PPSBn...

  • Page 53: Flash Security Protection Status Register - Cpsr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Security Protection Status Register – CPSR This register indicates the status of the Flash Memory Security protection. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader, which is active when any kind of reset occurs.

  • Page 54: Flash Vector Mapping Control Register - Vmcr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Vector Mapping Control Register – VMCR This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pin, BOOT, during the power-on reset period.

  • Page 55: Flash Manufacturer And Device Id Register - Mdid

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Manufacturer and Device ID Register – MDID This register specifies the manufacture ID and device part number information which can be used as the product identity. Offset: 0x180 Reset value: 0x0376_XXXX...

  • Page 56: Flash Page Number Status Register - Pnsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Page Number Status Register – PNSR This register specifies the page number of Flash memory. Offset: 0x184 Reset value: 0x0000_00XX PNSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...

  • Page 57: Flash Page Size Status Register - Pssr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Flash Page Size Status Register – PSSR This register specifies the page size in bytes. Offset: 0x188 Reset value: 0x0000_0400 PSSB Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO...

  • Page 58: Device Id Register - Didr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Device ID Register – DIDR This register specifies the device part number information which can be used as the product identity. Offset: 0x18C Reset value: 0x000X_XXXX Reserved Type/Reset Reserved ChipID Type/Reset X RO...

  • Page 59: Custom Id Register N - Cidrn, N = 0 ~3

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Custom ID Register n – CIDRn, n = 0 ~ 3 This register specifies the custom ID information which can be used as the custom identity. Offset: 0x310 (0) ~ 0x31C (3) Reset value: Various depending on Flash Manufacture Privilege Information Block.

  • Page 60: Power Control Unit (Pwrcu)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Power Control Unit (PWRCU) Introduction The power consumption can be regarded as one of the most important issues for many embedded system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power saving modes such as Sleep, Deep-Sleep1 and Deep-Sleep2 modes.

  • Page 61: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Three power domains: V and V 1.5 V power domains. DDIO DD15 ▄ Three power saving modes: Sleep, Deep-Sleep1 and Deep-Sleep2 modes. ▄ Internal Voltage regulator supplies 1.5 V voltage source.

  • Page 62: Figure 12. Power On Reset / Power Down Reset Waveform

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Hysteresis Time POR Delay Time RSTD RESET Figure 12. Power On Reset / Power Down Reset Waveform Low Voltage Detector / Brown Out Detector The Low Voltage Detector, LVD, can detect whether the supply voltage V...

  • Page 63: 1.5 V Power Domain

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 1.5 V Power Domain The main functions that include high speed internal oscillator, HSI, MCU core logic, AHB / APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered up, the POR will generate a reset sequence on 1.5 V power domain.

  • Page 64: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 11. Enter / Exit Power Saving Modes Mode Entry Mode Mode Exit LDOOFF DMOSON Instruction SLEEPDEEP WFI: Any interrupt WFE: Sleep Any wakeup event Any interrupt (NVIC on) or Any interrupt with SEVONPEND = 1 (NVIC off)

  • Page 65: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions Power Control Status Register – PWRSR This register indicates power control status. Offset: 0x100 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset Reserved WUPF1 WUPF Type/Reset 0 RC Reserved PORF Reserved...

  • Page 66: Power Control Register - Pwrcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Power Control Register – PWRCR This register provides power control bits for the different kinds of power saving modes. Offset: 0x104 Reset value: 0x0000_0000 Reserved Type/Reset Reserved WUP1TYPE WUP0TYPE Type/Reset 0 RW...
  • Page 67 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [10] WUP1EN External WAKEUP1 Pin Enable 0: Disable WAKEUP1 pin function 1: Enable WAKEUP1 pin function The Software can set the WUP1EN bit as 1 to enable the WAKEUP1 pin function before entering the power saving mode.

  • Page 68: Low Voltage / Brown Out Detect Control And Status Register - Lvdcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions LDOLCM LDO Low Current Mode 0: The LDO is operated in normal current mode 1: The LDO is operated in low current mode Note: This bit is only available when CPU is in the run mode. The LDO output current capability will be limited at 10 mA below and lower static current when the LDOLCM bit is set.
  • Page 69 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [19] LVDF Low Voltage Detect Status Flag 0: V is higher than the specific voltage level 1: V is equal to or lower than the specific voltage level When the LVD condition occurs, the LVDF flag will be asserted. When the LVDF flag is asserted, an LVD interrupt will be generated for CPU if the LVDIWEN bit is set to 1.

  • Page 70: Clock Control Unit (Ckcu)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Control Unit (CKCU) Introduction The Clock Control unit, CKCU, provides functions of high speed internal RC oscillator, HSI, High speed external crystal oscillator, HSE, Low speed internal RC oscillator, LSI, Low speed external crystal oscillator, LSE, HSE clock monitor, clock prescaler, clock multiplexer and clock gating.

  • Page 71: Figure 13. Ckcu Block Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 HSI Auto CK_LSE Trimming Prescaler Divider Controller CK_IN CK_REF 1 ~ 32 CKREFPRE CKREFEN 20 MHz HSI RC STCLK (to SysTick) HSIEN SW[2:0] CK_GPIO GPIOAEN (to GPIO port) 4 ~ 20 MHz...

  • Page 72: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ 4 ~ 20 MHz external crystal oscillator (HSE) ▄ Internal 20 MHz RC oscillator (HSI) with configuration option calibration and custom trimming capability. ▄ 32,768 Hz external crystal oscillator (LSE) for Watchdog Timer, RTC or system clock.

  • Page 73: High Speed Internal Rc Oscillator - Hsi

    The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by HOLTEK for ±2 % accuracy at V = 5 V and T = 25˚C.

  • Page 74: Figure 15. Hsi Auto Trimming Block Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Auto Trimming HSI Block Diagram Fine-Trimming Write Register ATCEN Counter Auto Trimming Register Controller TMSEL External pin (CKIN) 1 kHz /1.024 kHz 32.768 kHz REFCLKSEL Fine-Trimming Factory Read Register Trimming Bits Fine [7:0]...

  • Page 75: Low Speed External Crystal Oscillator - Lse

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Low Speed External Crystal Oscillator – LSE The low speed external crystal or ceramic resonator oscillator with 32.768 kHz frequency produces a low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock.

  • Page 76: Hse Clock Monitor

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 If any following action takes effect, the HSI is always under enable state. ▄ Enable Clock monitor. (CKMEN) ▄ Configure clock switch register bits to select the HSI. (SW) ▄ Configure HSI enable register bit to 1. (HSIEN) If any following action takes effect, the HSE is always under enable state.

  • Page 77: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the CKCU register and reset value. Table 15. CKCU Register Map Register Offset Description Reset Value GCFGR 0x000 Global Clock Configuration Register 0x0000_0002 GCCR 0x004 Global Clock Control Register...

  • Page 78: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions Global Clock Configuration Register – GCFGR This register specifies the low power mode status and clock source for CKOUT. Offset: 0x000 Reset value: 0x0000_0002 LPMOD Reserved Type/Reset 0 RO 0 RO...

  • Page 79: Global Clock Control Register - Gccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Global Clock Control Register – GCCR This register specifies the clock enable bits. Offset: 0x004 Reset value: 0x0000_0803 Reserved Type/Reset Reserved PSRCEN CKMEN Type/Reset 0 RW Reserved HSIEN HSEEN Reserved HSEGAIN Type/Reset...
  • Page 80 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions HSEGAIN External High Speed Clock Gain Selection 0: HSE low gain mode 1: HSE high gain mode [2:0] System Clock Switch 010: CK_HSE as system clock 011: CK_HSI as system clock...

  • Page 81: Global Clock Status Register - Gcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Global Clock Status Register – GCSR This register indicates the clock ready status. Offset: 0x008 Reset value: 0x0000_0028 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved LSIRDY LSERDY HSIRDY HSERDY Reserved Type/Reset 1 RO...

  • Page 82: Global Clock Interrupt Register - Gcir

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Global Clock Interrupt Register – GCIR This register specifies interrupt enable and flag bits. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved CKSIE Type/Reset Reserved Type/Reset Reserved CKSF Type/Reset Bits Field Descriptions...

  • Page 83: Ahb Configuration Register - Ahbcfgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 AHB Configuration Register – AHBCFGR This register specifies frequency of system clock. Offset: 0x020 Reset value: 0x0000_0001 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved AHBPRE Type/Reset 0 RW 0 RW Bits Field...

  • Page 84: Ahb Clock Control Register - Ahbccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 AHB Clock Control Register – AHBCCR This register specifies clock enable bits of AHB. Offset: 0x024 Reset value: 0x0000_0065 Reserved DIVEN Type/Reset Reserved PCEN PBEN PAEN Type/Reset 0 RW 0 RW Reserved...

  • Page 85: Apb Configuration Register - Apbcfgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions BMEN Bus Matrix Clock Enable 0: Bus Matrix clock is automatically disabled by hardware during Sleep mode 1: Bus Matrix clock is always enabled during Sleep mode Set and reset by software. Users can set BMEN as 0 to reduce power consumption if the bus matrix is unused during Sleep mode.

  • Page 86: Apb Clock Control Register 0 - Apbccr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Clock Control Register 0 – APBCCR0 This register specifies clock enable bits of APB peripherals. Offset: 0x02C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIEN AFIOEN Reserved UR1EN UR0EN Reserved USREN...

  • Page 87: Apb Clock Control Register 1 - Apbccr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions I2C1EN C1 Clock Enable 0: I C1 clock is disabled 1: I C1 clock is enabled Set and reset by software. I2C0EN C0 Clock Enable 0: I C0 clock is disabled...
  • Page 88 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [12] PWM0EN PWM0 Clock Enable 0: PWM0 clock is disabled 1: PWM0 clock is enabled Set and reset by software. GPTMEN GPTM Clock Enable 0: GPTM clock is disabled 1: GPTM clock is enabled Set and reset by software.

  • Page 89: Clock Source Status Register - Ckst

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Source Status Register – CKST This register specifies status of clock source. Offset: 0x034 Reset value: 0x0100_0003 Reserved HSIST Type/Reset 0 RO 0 RO Reserved HSEST Type/Reset 0 RO Reserved Type/Reset...

  • Page 90: Apb Peripheral Clock Selection Register 0 - Apbpcsr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Peripheral Clock Selection Register 0 – APBPCSR0 This register specifies APB peripheral clock prescaler selection. Offset: 0x038 Reset value: 0x0000_0000 UR1PCLK UR0PCLK Reserved USRPCLK Type/Reset 0 RW 0 RW 0 RW...
  • Page 91 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [15:14] BFTM1PCLK BFTM1 Peripheral Clock Selection 00: PCLK = CK_AHB 01: PCLK = CK_AHB / 2 10: PCLK = CK_AHB / 4 11: PCLK = CK_AHB / 8 PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock...

  • Page 92: Apb Peripheral Clock Selection Register 1 - Apbpcsr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Peripheral Clock Selection Register 1 – APBPCSR1 This register specifies APB peripheral clock prescaler selection. Offset: 0x03C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset VDDRPCLK WDTRPCLK Reserved Type/Reset 0 RW 0 RW...

  • Page 93: Hsi Control Register - Hsicr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 HSI Control Register – HSICR This register is to control the frequency trimming of HSI RC oscillation. Offset: 0x040 Reset value: 0xXXXX_0000 where X is undefined Reserved HSICOARSE Type/Reset X RO X RO...

  • Page 94: Hsi Auto Trimming Counter Register - Hsiatcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions ATCEN ATC Enable 0: Disable Auto Trimming Controller 1: Enable Auto Trimming Controller TRIMEN Trimming Enable 0: HSI Trimming is disable 1: HSI Trimming is enable The bit enables the HSI RC oscillator trimming function by ATC hardware or user programming.

  • Page 95: Apb Peripheral Clock Selection Register 2 - Apbpcsr2

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Peripheral Clock Selection Register 2 – APBPCSR2 This register specifies APB peripheral clock prescaler selection. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved PWM1PCLK PWM0PCLK Type/Reset 0 RW 0 RW Reserved...

  • Page 96: Mcu Debug Control Register - Mcudbgcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 MCU Debug Control Register – MCUDBGCR This register specifies debug control of MCU. Offset: 0x304 Reset value: 0x0000_0000 DBPWM1 DBPWM0 Reserved Type/Reset 0 RW Reserved DBUR1 DBUR0 DBBFTM1 DBBFTM0 Type/Reset 0 RW...
  • Page 97 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [13] DBI2C1 C1 Debug Mode Enable 0: Same behavior as in normal mode 1: I C1 timeout is frozen when the core is halted Set and reset by software.

  • Page 98: Reset Control Unit (Rstcu)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Reset Control Unit (RSTCU) Introduction The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and APB unit reset. The power on reset, known as a cold reset, resets the full system during a power up.

  • Page 99: Functional Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Descriptions Power On Reset The Power on reset, POR, is generated by either an external reset or the internal reset generator. Both types have an internal filter to prevent glitches from causing erroneous reset operations. By referring to Figure 18, the POR15 active low signal will be de-asserted when the internal LDO voltage regulator is ready to provide a 1.5 V power.

  • Page 100: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the RSTCU registers and reset values. Table 16. RSTCU Register Map Register Offset Description Reset Value GRSR 0x100 Global Reset Status Register 0x0000_0008 AHBPRSTR 0x104 AHB Peripheral Reset Register...

  • Page 101: Ahb Peripheral Reset Register - Ahbprstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions NVICRSTF NVIC Reset Flag 0: No NVIC asserting system reset occurred 1: NVIC asserting system reset occurred This bit is set by hardware when a system reset occurs and reset by writing 1 into it or by hardware when a power on reset occurs.

  • Page 102: Apb Peripheral Reset Register 0 - Apbprstr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 APB Peripheral Reset Register 0 – APBPRSTR0 This register specifies several APB peripherals software reset control bits. Offset: 0x108 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTIRST AFIORST Reserved UR1RST UR0RST Reserved...

  • Page 103: Apb Peripheral Reset Register 1 - Apbprstr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions I2C1RST C1 Reset Control 0: No reset 1: Reset I This bit is set by software and cleared to 0 by hardware automatically. I2C0RST C0 Reset Control 0: No reset 1: Reset I This bit is set by software and cleared to 0 by hardware automatically.
  • Page 104 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [12] PWM0RST PWM0 Reset Control 0: No reset 1: Reset PWM0 This bit is set by software and cleared to 0 by hardware automatically. GPTMRST GPTM Reset Control 0: No reset 1: Reset GPTM This bit is set by software and cleared to 0 by hardware automatically.

  • Page 105: General Purpose I/O (Gpio)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 General Purpose I/O (GPIO) Introduction There are up to 40 General Purpose I/O port, GPIO, named PA0 ~ PA15, PB0 ~ PB15 and PC0 ~ PC7 for the device to implement the logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirement of specific applications.

  • Page 106: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Input / output direction control ▄ Input weak pull-up / pull-down control ▄ Output push-pull / open-drain enable control ▄ Output set / reset control ▄ Output drive current selection ▄...

  • Page 107: Table 17. Afio, Gpio And I/O Pad Control Signal True Table

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 PxCFGn Input DMUX Output AFIO Control IOPAD AFIO ADEN PxDOUTn PxDINn PxRSTn PxDVn PxINENn PxSETn PxODn PxDIRn PxPDn PxPUn GPIO Figure 20. AFIO / GPIO Control Signal PxDINn / PxDOUTn (x = A ~ C): Data Input / Data Output...

  • Page 108: Gpio Locking Mechanism

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 GPIO Locking Mechanism The GPIO also offers a lock function to lock the port until a reset event occurs. The PxLOCKR (x = A ~ C) registers are used to lock the port x and lock control options. The value 0x5FA0 is...

  • Page 109: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Offset Description Reset Value PCLOCKR 0x018 Port C Lock Register 0x0000_0000 PCDINR 0x01C Port C Data Input Register 0x0000_0000 PCDOUTR 0x020 Port C Data Output Register 0x0000_0000 PCSRR 0x024 Port C Output Set and Reset Control Register...

  • Page 110: Port A Input Function Enable Control Register - Painer

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Input Function Enable Control Register – PAINER This register is used to enable or disable the GPIO Port A input function. Offset: 0x004 Reset value: 0x0000_0200 Reserved Type/Reset Reserved Type/Reset...

  • Page 111: Port A Pull-Up Selection Register - Papur

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Pull-Up Selection Register – PAPUR This register is used to enable or disable the GPIO Port A pull-up function. Offset: 0x008 Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PAPU Type/Reset...

  • Page 112: Port A Pull-Down Selection Register - Papdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Pull-Down Selection Register – PAPDR This register is used to enable or disable the GPIO Port A pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAPD Type/Reset...

  • Page 113: Port A Open-Drain Selection Register - Paodr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Open-Drain Selection Register – PAODR This register is used to enable or disable the GPIO Port A open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PAOD...

  • Page 114: Port A Output Drive Current Selection Register - Padrvr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Output Drive Current Selection Register – PADRVR This register specifies the GPIO Port A output driving current. Offset: 0x014 Reset value: 0x0000_0000 PADV15 PADV14 PADV13 PADV12 Type/Reset 0 RW 0 RW...

  • Page 115: Port A Lock Register - Palockr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Lock Register – PALOCKR This register specifies the GPIO Port A lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PALKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 116: Port A Data Input Register - Padinr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Data Input Register – PADINR This register specifies the GPIO Port A input data. Offset: 0x01C Reset value: 0x0000_3200 Reserved Type/Reset Reserved Type/Reset PADIN Type/Reset 0 RO 0 RO 1 RO...

  • Page 117: Port A Output Set / Reset Control Register - Pasrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Output Set / Reset Control Register – PASRR This register is used to set or reset the corresponding bit of the GPIO Port A output data. Offset: 0x024 Reset value: 0x0000_0000...

  • Page 118: Port A Output Reset Register - Parr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port A Output Reset Register – PARR This register is used to reset the corresponding bit of the GPIO Port A output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 119: Port B Data Direction Control Register - Pbdircr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Data Direction Control Register – PBDIRCR This register is used to control the direction of GPIO Port B pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 120: Port B Input Function Enable Control Register - Pbiner

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Input Function Enable Control Register – PBINER This register is used to enable or disable the GPIO Port B input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 121: Port B Pull-Up Selection Register - Pbpur

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Pull-Up Selection Register – PBPUR This register is used to enable or disable the GPIO Port B pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPU Type/Reset...

  • Page 122: Port B Pull-Down Selection Register - Pbpdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Pull-Down Selection Register – PBPDR This register is used to enable or disable the GPIO Port B pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBPD Type/Reset...

  • Page 123: Port B Open-Drain Selection Register - Pbodr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Open-Drain Selection Register – PBODR This register is used to enable or disable the GPIO Port B open-drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBOD Type/Reset...

  • Page 124: Port B Output Drive Current Selection Register - Pbdrvr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Output Drive Current Selection Register – PBDRVR This register specifies the GPIO Port B output driving current. Offset: 0x014 Reset value: 0x0000_0000 PBDV15 PBDV14 PBDV13 PBDV12 Type/Reset 0 RW 0 RW...

  • Page 125: Port B Lock Register - Pblockr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Lock Register – PBLOCKR This register specifies the GPIO Port B lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PBLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 126: Port B Data Input Register - Pbdinr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Data Input Register – PBDINR This register specifies the GPIO Port B input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PBDIN Type/Reset 0 RO 0 RO 0 RO...

  • Page 127: Port B Output Set / Reset Control Register - Pbsrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Output Set / Reset Control Register – PBSRR This register is used to set or reset the corresponding bit of the GPIO Port B output data. Offset: 0x024 Reset value: 0x0000_0000...

  • Page 128: Port B Output Reset Register - Pbrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port B Output Reset Register – PBRR This register is used to reset the corresponding bit of the GPIO Port B output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 129: Port C Data Direction Control Register - Pcdircr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Data Direction Control Register – PCDIRCR This register is used to control the direction of GPIO Port C pin as input or output. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 130: Port C Input Function Enable Control Register - Pciner

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Input Function Enable Control Register – PCINER This register is used to enable or disable the GPIO Port C input function. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 131: Port C Pull-Up Selection Register - Pcpur

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Pull-Up Selection Register – PCPUR This register is used to enable or disable the GPIO Port C pull-up function. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...

  • Page 132: Port C Pull-Down Selection Register - Pcpdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Pull-Down Selection Register – PCPDR This register is used to enable or disable the GPIO Port C pull-down function. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset...

  • Page 133: Port C Open Drain Selection Register - Pcodr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Open Drain Selection Register – PCODR This register is used to enable or disable the GPIO Port C open drain function. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 134: Port C Output Current Drive Selection Register - Pcdrvr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Output Current Drive Selection Register – PCDRVR This register specifies the GPIO Port C output driving current. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PCDV7 PCDV6 PCDV5 PCDV4...

  • Page 135: Port C Lock Register - Pclockr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Lock Register – PCLOCKR This register specifies the GPIO Port C lock configuration. Offset: 0x018 Reset value: 0x0000_0000 PCLKEY Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 136: Port C Data Input Register - Pcdinr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Data Input Register – PCDINR This register specifies the GPIO Port C input data. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset PCDIN Type/Reset 0 RO 0 RO...

  • Page 137: Port C Output Set / Reset Control Register - Pcsrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Output Set / Reset Control Register – PCSRR This register is used to set or reset the corresponding bit of the GPIO Port C output data. Offset: 0x024 Reset value: 0x0000_0000...

  • Page 138: Port C Output Reset Register - Pcrr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Port C Output Reset Register – PCRR This register is used to reset the corresponding bit of the GPIO Port C output data. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset...

  • Page 139: Alternate Function Input / Output Control Unit (Afio)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Alternate Function Input / Output Control Unit (AFIO) Introduction In order to expand the flexibility of the GPIO or the usage of peripheral functions, each I/O pin can be configured to have up to sixteen different functions such as GPIO or IP functions by setting the GPxCFGLR or GPxCFGHR register where x is the different port name.

  • Page 140: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ APB slave interface for register access ▄ EXTI source selection ▄ Configurable pin function for each GPIO, up to sixteen alternative functions on each pin ▄ AFIO lock mechanism Functional Descriptions External Interrupt Pin Selection The GPIO pins are connected to the 16 EXTI lines as shown in the accompanying figure.

  • Page 141: Alternate Function

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Alternate Function Up to sixteen alternative functions can be chosen for each I/O pad by setting the PxCFGn [3:0] field in the GPxCFGLR or GPxCFGHR (n = 0 ~ 15, x = A ~ C) registers. If the pin is selected as unavailable item which is noted as “N/A”...

  • Page 142: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions EXTI Source Selection Register 0 – ESSR0 This register specifies the I/O selection of EXTI0 ~ EXTI7. Offset: 0x000 Reset value: 0x0000_0000 EXTI7PIN EXTI6PIN Type/Reset 0 RW 0 RW 0 RW...

  • Page 143: Exti Source Selection Register 1 - Essr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Source Selection Register 1 – ESSR1 This register specifies the I/O selection of EXTI8 ~ EXTI15. Offset: 0x004 Reset value: 0x0000_0000 EXTI15PIN EXTI14PIN Type/Reset 0 RW 0 RW 0 RW 0 RW...

  • Page 144: Gpio X Configuration Low Register - Gpxcfglr, X = A, B, C

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C This low register specifies the alternate function of GPIO Port x, x = A, B, C. Offset: 0x020, 0x028, 0x030...

  • Page 145: Gpio X Configuration High Register - Gpxcfghr, X = A, B, C

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 GPIO x Configuration High Register – GPxCFGHR, x = A, B, C This high register specifies the alternate function of GPIO Port x. x = A, B, C. Offset: 0x024, 0x02C, 0x034...

  • Page 146: Nested Vectored Interrupt Controller (Nvic)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Nested Vectored Interrupt Controller (NVIC) Introduction In order to reduce the latency and increase the interrupt processing efficiency, a tightly coupled integrated section, which is named as Nested Vectored Interrupt Controller (NVIC) is provided by the Cortex -M0+.

  • Page 147: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Interrupt Exception Exception Vector Priority Description Number Number Type Address Reserved — 0x078 — PWM0 Configurable 0x07C PWM0 global interrupt PWM1 Configurable 0x080 PWM1 global interrupt BFTM0 Configurable 0x084 BFTM0 global interrupt...

  • Page 148: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Function Descriptions SysTick Calibration The SysTick Calibration Value Register (SYST_CALIB) is provided by the NVIC to give a reference time base of 1ms for the RTOS tick timer or other purposes. The TENMS field in the SYST_CALIB register has a fixed value of 2500 which is the counter reload value to indicate 1 ms when the clock source comes from the SysTick reference input clock STCLK with a frequency of 2.5 MHz (20 MHz...

  • Page 149: External Interrupt / Event Controller (Exti)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 External Interrupt / Event Controller (EXTI) Introduction The External Interrupt / Event Controller, EXTI, comprises 16 edge detectors which can generate a wakeup event or interrupt requests independently. In the interrupt mode there are five trigger...

  • Page 150: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Function Descriptions Wakeup Event Management In order to wakeup the system from the power saving mode, the EXTI controller provides a function which can monitor external events and send them to the CPU core and the Clock Control Unit, CKCU.

  • Page 151: External Interrupt / Event Line Mapping

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 External Interrupt / Event Line Mapping All GPIO pins can be selected as EXTI trigger sources by configuring the EXTInPIN [3:0] field in the AFIO ESSRn (n = 0 ~ 1) register to trigger an interrupt or event. Refer to the AFIO section for more details.

  • Page 152: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the EXTI registers and reset values. Table 23. EXTI Register Map Register Offset Description Reset Value EXTICFGR0 0x000 EXTI Interrupt 0 Configuration Register 0x0000_0000 EXTICFGR1 0x004...

  • Page 153: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions EXTI Interrupt n Configuration Register – EXTICFGRn, n = 0 ~ 15 This register is used to specify the debounce function and select the trigger type. Offset: 0x000 (0) ~ 0x03C (15)

  • Page 154: Exti Interrupt Control Register - Exticr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Control Register – EXTICR This register is used to control the EXTI interrupt. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EN EXTI14EN EXTI13EN EXTI12EN EXTI11EN EXTI10EN EXTI9EN EXTI8EN...

  • Page 155: Exti Interrupt Edge Flag Register - Extiedgeflgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR This register is used to indicate if an EXTI edge has been detected. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDF EXTI14EDF EXTI13EDF EXTI12EDF EXTI11EDF EXTI10EDF EXTI9EDF EXTI8EDF...

  • Page 156: Exti Interrupt Edge Status Register - Extiedgesr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Edge Status Register – EXTIEDGESR This register indicates the polarity of a detected EXTI edge. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15EDS EXTI14EDS EXTI13EDS EXTI12EDS EXTI11EDS EXTI10EDS EXTI9EDS EXTI8EDS...

  • Page 157: Exti Interrupt Software Set Command Register - Extisscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Software Set Command Register – EXTISSCR This register is used to activate the EXTI interrupt. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15SC EXTI14SC EXTI13SC EXTI12SC EXTI11SC EXTI10SC...

  • Page 158: Exti Interrupt Wakeup Control Register - Extiwakupcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR This register is used to control the EXTI interrupt and wakeup function. Offset: 0x050 Reset value: 0x0000_0000 EVWUPIEN Reserved Type/Reset Reserved Type/Reset EXTI15WEN EXTI14WEN EXTI13WEN EXTI12WEN EXTI11WEN EXTI10WEN EXTI9WEN EXTI8WEN...

  • Page 159: Exti Interrupt Wakeup Polarity Register - Extiwakuppolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR This register is used to select the EXTI line interrupt wakeup polarity. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WPOL EXTI14WPOL EXTI13WPOL EXTI12WPOL EXTI11WPOL EXTI10WPOL EXTI9WPOL EXTI8WPOL...

  • Page 160: Exti Interrupt Wakeup Flag Register - Extiwakupflg

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG This register is the EXTI interrupt wakeup flag register. Offset: 0x058 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset EXTI15WFL EXTI14WFL EXTI13WFL EXTI12WFL EXTI11WFL EXTI10WFL EXTI9WFL...

  • Page 161: Analog To Digital Converter (Adc)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Analog to Digital Converter (ADC) Introduction A 12-bit multi-channel Analog to Digital Converter is integrated in the device. There are a total of 14 multiplexed channels including 12 external channels on which the external analog signal can be supplied and 2 internal channels.

  • Page 162: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ 12-bit SAR ADC engine ▄ Up to 1 Msps conversion rate ▄ 12 external analog input channels ▄ 2 internal analog input channels for reference voltage detection ▄ Programmable sampling time for conversion channel ▄...

  • Page 163: Function Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Function Descriptions ADC Clock Setup The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.

  • Page 164: Figure 27. One Shot Conversion Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Conversion (ex: Sequence Length=8) Cycle Cycle Start of Conversion Single sample End of Conversion Cycle End of Conversion Figure 27. One Shot Conversion Mode Continuous Conversion Mode In Continuous Conversion Mode, repeated conversion cycle will start automatically without requiring additional A/D start trigger signals after a channels group conversion has completed.
  • Page 165 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Discontinuous Conversion Mode The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCR register is set to 0x3. The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1.

  • Page 166: Start Conversion On External Event

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 (ex: Sequence Length=8, Subgroup Length=3 ) Discontinuous Conversion Mode Cycle Cycle Subgroup 0 Subgroup 1 Subgroup 2 Subgroup 0 Start of Conversion Single sample End of Conversion Subgroup End of Conversion Cycle End of Conversion Figure 29.

  • Page 167: Sampling Time Setting

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Sampling Time Setting The conversion channel can be programmed the sampling time according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor of the converter to the input voltage level.

  • Page 168: Interrupts

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Interrupts When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three kinds of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion.

  • Page 169: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the A/D Converter registers and reset values. Table 25. A/D Converter Register Map Register Offset Description Reset Value ADCCR 0x000 ADC Conversion Control Register 0x0000_0000 ADCLST0...

  • Page 170: Register Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions ADC Conversion Control Register – ADCCR This register specifies the mode setting, sequence length and subgroup length of ADC conversion mode. Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to an idle state.
  • Page 171 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [1:0] ADMODE ADC Conversion Mode ADMODE [1:0] Mode Descriptions After a start trigger, the conversion will be One shot mode executed on the specific channels for the whole conversion sequence once.

  • Page 172: Adc Conversion List Register 0 - Adclst0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Conversion List Register 0 – ADCLST0 This register specifies the conversion sequence order No.0 ~ No.3 of the ADC. Offset: 0x004 Reset value: 0x0000_0000 Reserved ADSEQ3 Type/Reset 0 RW 0 RW...

  • Page 173: Adc Conversion List Register 1 - Adclst1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Conversion List Register 1 – ADCLST1 This register specifies the conversion sequence order No.4 ~ No.7 of the ADC. Offset: 0x008 Reset value: 0x0000_0000 Reserved ADSEQ7 Type/Reset 0 RW 0 RW...

  • Page 174: Adc Input Sampling Time Register - Adcstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Input Sampling Time Register – ADCSTR This register specifies the A/D converter input channel sampling time. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset ADST Type/Reset 0 RW...

  • Page 175: Adc Conversion Data Register Y - Adcdry, Y = 0 ~ 7

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n = 0 ~ 1) registers.

  • Page 176: Adc Trigger Control Register - Adctcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Trigger Control Register – ADCTCR This register contains the ADC start conversion trigger enable bits. Offset: 0x070 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved ADEXTI ADSW Type/Reset 0 RW...

  • Page 177: Adc Trigger Source Register - Adctsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Trigger Source Register – ADCTSR This register contains the trigger source selection and the software trigger bit of the conversion. Offset: 0x074 Reset value: 0x0000_0000 Reserved TM1E TM0E Type/Reset 0 RW...

  • Page 178: Adc Watchdog Control Register - Adcwcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [11:8] ADEXTIS EXTI Trigger Source Selection of ADC Conversion 0x00: EXTI line 0 0x01: EXTI line 1 … 0x0F: EXTI line 15 Note that the EXTI line active edge to start an A/D conversion is determined in the External Interrupt / Event Control Unit, EXTI.
  • Page 179 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [19:16] ADLCH Lower Threshold Channel Status 0000: ADC_IN0 is lower than the lower threshold 0001: ADC_IN1 is lower than the lower threshold 1011: ADC_IN11 is lower than the lower threshold...

  • Page 180: Adc Watchdog Threshold Register - Adctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Watchdog Threshold Register – ADCTR This register specifies the upper and lower threshold of the ADC watchdog function. Offset: 0x07C Reset value: 0x0000_0000 Reserved ADUT Type/Reset 0 RW 0 RW 0 RW...

  • Page 181: Adc Interrupt Enable Register - Adcier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Interrupt Enable Register – ADCIER This register contains the ADC interrupt enable bits. Offset: 0x080 Reset value: 0x0000_0000 Reserved ADIEO Type/Reset Reserved ADIEU ADIEL Type/Reset 0 RW Reserved Type/Reset Reserved ADIEC...

  • Page 182: Adc Interrupt Raw Status Register - Adciraw

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Interrupt Raw Status Register – ADCIRAW This register contains the ADC interrupt raw status bits. Offset: 0x084 Reset value: 0x0000_0000 Reserved ADIRAWO Type/Reset Reserved ADIRAWU ADIRAWL Type/Reset 0 RO Reserved Type/Reset...

  • Page 183: Adc Interrupt Status Register - Adcisr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Interrupt Status Register – ADCISR This register contains the ADC interrupt status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.

  • Page 184: Adc Interrupt Clear Register - Adciclr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 ADC Interrupt Clear Register – ADCICLR This register provides the clear bits used to clear the interrupt raw and interrupt status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.

  • Page 185: General-Purpose Timer (Gptm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 General-Purpose Timer (GPTM) Introduction The General-Purpose Timer consists of one 16-bit up / down-counter, four 16-bit Capture / Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control / status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.

  • Page 186: Functional Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 ● Generation of PWM waveform – Edge and Center-aligned Mode ● Single Pulse Mode Output ▄ Encoder interface controller with two inputs using quadrature decoder ▄ Synchronization circuit to control the timer with external signals and to interconnect several timers together ▄...

  • Page 187: Figure 32. Down-Counting Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Down-Counting In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value.

  • Page 188: Figure 33. Center-Aligned Counting Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.

  • Page 189: Clock Controller

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...

  • Page 190: Trigger Controller

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.

  • Page 191: Slave Controller

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Slave Controller The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which can be selected by the SMSEL field in the MDCFR register.

  • Page 192: Figure 38. Gptm In Pause Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start / stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.

  • Page 193: Master Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master Controller The GPTMs and MCTMs can be linked together internally for timer synchronization or chaining. When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or MCTM, if exists, which is configured in the Slave Mode.

  • Page 194: Channel Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Controller The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading / writing the preload register.

  • Page 195: Figure 43. Input Capture Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Capture Counter Value Transferred to CHxCCR When the channel is used as a capture input, the counter value is captured into the Channel Capture / Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly.

  • Page 196: Figure 44. Pwm Pulse Width Measurement Example

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the GT_ CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1.

  • Page 197: Input Stage

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Input Stage The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals.

  • Page 198: Figure 46. Channel 2 And Channel 3 Input Stages

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 TRCED CH2CCS CLKIN GT_CH2 TI2FP Filter TI2S2 Edge TI2S2ED sampling TI2FN Detection CH2PSC TI2F CH2PRESCALER CH2P CH2CAP Event TI3S2 Edge TI3S2ED CH2PSC Detection TI2S3 Edge TI2S3ED Detection CH3P CH3PSC TI3FP GT_CH3 CH3PRESCALER...

  • Page 199: Quadrature Decoder

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Quadrature Decoder The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_ CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x1, 0x2 or 0x3.

  • Page 200: Table 26. Counting Direction And Encoding Signals

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 26. Counting Direction and Encoding Signals TI0S0 TI1S1 Counting Mode Level Rising Falling Rising Falling TI1S1 = High Down — — Counting on TI0 only (SMSEL = 0x1) TI1S1 = Low Down —...

  • Page 201: Output Stage

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Output Stage The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding CHxOCFR, CHPOLR and CHCTR registers.

  • Page 202: Figure 51. Toggle Mode Channel Output Reference Signal - Chxpre = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value CHxOM=0x3, CHxPRE=0 (Output toggle, preload disable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF (Update Event) Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 0...

  • Page 203: Figure 53. Pwm Mode Channel Output Reference Signal And Counter In Up-Counting Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value Counter Value Counter Value CHxCCR CHxCCR CHxCCR = 0x0000 CHxOM = 0x6 100% CHxOREF CHxOREF CHxOREF CHxCCIF CHxCCIF CHxCCIF CHxOM = 0x7 CHxOREF Figure 53. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode...

  • Page 204: Figure 55. Pwm Mode Channel Output Reference Signal And Counter In Centre-Aligned Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 CRR = 5 CMSEL = 0x1 Up-counting Down-counting CHxCCR = 3 CHxCCIF CHxCCR = 4 CHxCCIF CHxCCR >= 5 100% CHxCCIF CHxCCR = 0 CHxCCIF Figure 55. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode Rev.

  • Page 205: Update Management

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.

  • Page 206: Single Pulse Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.

  • Page 207: Figure 58. Immediate Active Mode Minimum Delay

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.

  • Page 208: Asymmetric Pwm Mode

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.

  • Page 209: Timer Interconnection

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.

  • Page 210: Figure 61. Triggering Mctm With Gptm Update Event

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Using One Timer to Trigger Another Timer Start Counting ▄ Configure GPTM to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x2). ▄...

  • Page 211: Figure 62. Trigger Gptm And Mctm With The Gptm Ch0 Input

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Starting Two Timers Synchronously in Response to an External Trigger ▄ Configure GPTM to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x1). ▄...

  • Page 212: Trigger Adc Start

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the GPTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.

  • Page 213: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the GPTM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved CKDIV Type/Reset 0 RW...

  • Page 214: Timer Mode Configuration Register - Mdcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions UEVDIS Update event Disable control 0: Enable the update event request by one of following events: - Counter overflow / underflow - Setting the UEVG bit - Update generation through the slave mode...
  • Page 215 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
  • Page 216 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions The prescaler is clocked directly by the internal Disable mode clock. The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to Quadrature drive the counter prescaler.

  • Page 217: Timer Trigger Configuration Register - Trcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of GPTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...

  • Page 218: Timer Counter Register - Ctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Counter Register – CTR This register specifies the timer enable bit (TME) and CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE...

  • Page 219: Channel 0 Input Configuration Register - Ch0Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...

  • Page 220: Channel 1 Input Configuration Register - Ch1Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
  • Page 221 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture / Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal...

  • Page 222: Channel 2 Input Configuration Register - Ch2Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...

  • Page 223: Channel 3 Input Configuration Register - Ch3Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divided ratio used to sample the TI2 signal. The Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.

  • Page 224: Channel 0 Output Configuration Register - Ch0Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] CH3CCS Channel 3 Capture / Compare Selection 00: Channel 3 is configured as an output 01: Channel 3 is configured as an input derived from the TI3 signal...
  • Page 225 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH0IMAE Channel 0 Immediate Active Enable 0: No action 1: Single pulse Immediate Active Mode is enabled The CH0OREF will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values.

  • Page 226: Channel 1 Output Configuration Register - Ch1Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
  • Page 227 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 228: Channel 2 Output Configuration Register - Ch2Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
  • Page 229 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 230: Channel 3 Output Configuration Register - Ch3Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
  • Page 231 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 232: Channel Control Register - Chctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...

  • Page 233: Channel Polarity Configuration Register - Chpolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved...

  • Page 234: Timer Interrupt Control Register - Dictr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CH3CCIE CH2CCIE...

  • Page 235: Timer Event Generator Register - Evgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CH3CCG CH2CCG CH1CCG...

  • Page 236: Timer Interrupt Status Register - Intsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH1CCG Channel 1 Capture / Compare Generation A Channel 1 capture / compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action...
  • Page 237 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions UEVIF Update Event Interrupt Flag This bit is set by hardware on an update event and is cleared by software. 0: No update event occurs 1: Update event occurs...

  • Page 238: Timer Counter Register - Cntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH1CCIF Channel 1 Capture / Compare Interrupt Flag - Channel 1 is configured as an output: 0: No match event occurs 1: The contents of the counter CNTR have matched the contents of the CH1CCR...

  • Page 239: Timer Prescaler Register - Pscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...

  • Page 240: Timer Counter Reload Register - Crr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...

  • Page 241: Channel 0 Capture / Compare Register - Ch0Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Capture / Compare Register – CH0CCR This register specifies the timer channel 0 capture / compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW...

  • Page 242: Channel 1 Capture / Compare Register - Ch1Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Capture / Compare Register – CH1CCR This register specifies the timer channel 1 capture / compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW...

  • Page 243: Channel 2 Capture / Compare Register - Ch2Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Capture / Compare Register – CH2CCR This register specifies the timer channel 2 capture / compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW...

  • Page 244: Channel 3 Capture / Compare Register - Ch3Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Capture / Compare Register – CH3CCR This register specifies the timer channel 3 capture / compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW...

  • Page 245: Channel 0 Asymmetric Compare Register - Ch0Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...

  • Page 246: Channel 2 Asymmetric Compare Register - Ch2Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...

  • Page 247: Pulse Width Modulator (Pwm)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pulse Width Modulator (PWM) Introduction The Pulse Width Modulator consists of one 16-bit up / down-counter, four 16-bit Compare Registers (CRs), one 16-bit Counter Reload Register (CRR) and several control / status registers. It can be used for a variety of purposes including general timer and output waveform generation such as single pulse generation or PWM output.

  • Page 248: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ 16-bit up / down auto-reload counter ▄ 16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...

  • Page 249: Figure 65. Down-Counting Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Down-Counting In this mode the counter counts continuously from the counter reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter reload value.

  • Page 250: Figure 66. Center-Aligned Counting Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.

  • Page 251: Clock Controller

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Controller The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f used to drive the counter prescaler.

  • Page 252: Trigger Controller

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register.

  • Page 253: Slave Controller

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Slave Controller The PWM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register.

  • Page 254: Figure 71. Pwm In Pause Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start / stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset.

  • Page 255: Master Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master Controller The PWMs and TMs can be linked together internally for timer synchronization or chaining. When one PWM is configured to be in the Master Mode, the PWM Master Controller will generate a...

  • Page 256: Channel Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Controller The PWM has four independent channels which can be used as compare match outputs. Each compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading / writing preload register.

  • Page 257: Figure 77. Toggle Mode Channel Output Reference Signal (Chxpre = 0)

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Output Reference Signal When the PWM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM bit setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCR register.

  • Page 258: Figure 78. Toggle Mode Channel Output Reference Signal (Chxpre = 1)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value CHxOM=0x3, CHxPRE=1 (Output toggle, preload enable) CHxCR (New value 2) CHxCR (New value 3) CHxCR (New value 1) CHxCR Time Update CHxCR value CHxOREF (Update Event) Figure 78. Toggle Mode Channel Output Reference Signal (CHxPRE = 1)

  • Page 259: Figure 80. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value Counter Value CHxCR CHxCR CHxOM = 0x6 100% CHxOREF CHxOREF CHxCIF CHxCIF CHxOM = 0x7 CHxOREF Figure 80. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode CMSEL= 0x1...

  • Page 260: Update Management

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Update Management The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.

  • Page 261: Figure 83. Single Pulse Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value CHxCR Counter Counter stopped reinitialized and held Time TME bit Trigger by STI Cleared by Cleared by S/W Trigger by S/W Update Event CHxOREF delay delay (PWM1) CHxIMAE=0 delay delay...

  • Page 262: Figure 84. Immediate Active Mode Minimum Delay

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register.

  • Page 263: Asymmetric Pwm Mode

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCR and CHxACR register.

  • Page 264: Figure 86. Pausing Pwm1 Using The Pwm0 Ch0Oref Signal

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master PWM0 CLKIN PWM0 CH0OREF PWM0 CNTR Slave PWM1 PWM1 CNTR PWM1 TEVIF Software clearing Figure 86. Pausing PWM1 using the PWM0 CH0OREF Signal Using one timer to trigger another timer start counting ▄...

  • Page 265: Trigger Peripherals Start

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Starting two timers synchronously with the master enable MTO signal trigger ▄ Configure PWM0 to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x1).

  • Page 266: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the PWM registers and reset values. Table 31. PWM Register Map Register Offset Description Reset Value CNTCFR 0x000 Timer Counter Configuration Register 0x0000_0000 MDCFR 0x004 Timer Mode Configuration Register...

  • Page 267: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions Timer Counter Configuration Register – CNTCFR This register specifies the PWM counter configuration. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CMSEL Type/Reset 0 RW Reserved Type/Reset Reserved UGDIS UEVDIS...

  • Page 268: Timer Mode Configuration Register - Mdcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Mode Configuration Register – MDCFR This register specifies the PWM master and slave mode selection and single pulse mode. Offset: 0x004 Reset value: 0x0000_0000 Reserved SPMSET Type/Reset Reserved MMSEL Type/Reset 0 RW...
  • Page 269 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. MMSEL [2:0] Mode Descriptions...
  • Page 270 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [11:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions Disable mode The prescaler is clocked directly by the internal clock. — Reserved — Reserved — Reserved The counter value restarts from 0 or the CRR shadow...

  • Page 271: Timer Trigger Configuration Register - Trcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of PWM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...

  • Page 272: Timer Counter Register - Ctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Counter Register – CTR This register specifies the timer enable bit (TME) and CRR buffer enable bit (CRBE). Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CRBE...

  • Page 273: Channel 0 Output Configuration Register - Ch0Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
  • Page 274 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 275: Channel 1 Output Configuration Register - Ch1Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
  • Page 276 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 277: Channel 2 Output Configuration Register - Ch2Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
  • Page 278 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 279: Channel 3 Output Configuration Register - Ch3Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
  • Page 280 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 281: Channel Control Register - Chctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Control Register – CHCTR This register contains the channel compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E Reserved CH2E Reserved...

  • Page 282: Channel Polarity Configuration Register - Chpolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Polarity Configuration Register – CHPOLR This register contains the channel compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P Reserved CH2P Reserved CH1P...

  • Page 283: Timer Interrupt Control Register - Dictr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVIE Reserved UEVIE Type/Reset Reserved CH3CIE CH2CIE...

  • Page 284: Timer Event Generator Register - Evgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved TEVG Reserved UEVG Type/Reset Reserved CH3CG CH2CG CH1CG...

  • Page 285: Timer Interrupt Status Register - Intsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH0CG Channel 0 Compare Generation A Channel 0 compare event can be generated by software setting this bit. It is cleared by hardware automatically. 0: No action 1: Compare event is generated on channel 0 Timer Interrupt Status Register –...

  • Page 286: Timer Counter Register - Cntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH2CIF Channel 2 Compare Interrupt Flag 0: No match event occurs 1: The content of the counter CNTR has matched the contents of the CH2CR register This flag is set by hardware when the counter value matches the CH2CR value except in the center-aligned mode.

  • Page 287: Timer Prescaler Register - Pscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...

  • Page 288: Channel 0 Compare Register - Ch0Cr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Compare Register – CH0CR This register specifies the timer channel 0 compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CV Type/Reset 0 RW 0 RW 0 RW...

  • Page 289: Channel 2 Compare Register - Ch2Cr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Compare Register – CH2CR This register specifies the timer channel 2 capture / compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CV Type/Reset 0 RW 0 RW...

  • Page 290: Channel 0 Asymmetric Compare Register - Ch0Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...

  • Page 291: Channel 2 Asymmetric Compare Register - Ch2Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...

  • Page 292: Basic Function Timer (Bftm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Basic Function Timer (BFTM) Introduction The Basic Function Timer Module, BFTM, is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes.

  • Page 293: Functional Description

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Description The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.

  • Page 294: One Shot Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 One Shot Mode By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program.

  • Page 295: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the BFTM registers and their reset values. Table 33. BFTM Register Map Register Offset Description Reset Value BFTMCR 0x000 BFTM Control Register 0x0000_0000 BFTMSR 0x004 BFTM Status Register...

  • Page 296: Bftm Status Register - Bftmsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 BFTM Status Register – BFTMSR This register specifies the BFTM status. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Bits Field Descriptions BFTM Compare Match Interrupt Flag...

  • Page 297: Bftm Counter Value Register - Bftmcntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 BFTM Counter Value Register – BFTMCNTR This register specifies the BFTM counter value. Offset: 0x008 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 298: Motor Control Timer (Mctm)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Motor Control Timer (MCTM) Introduction The Motor Control Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit Repetition Counter (REPR) and several control/status registers. It can be used for a variety of purposes which include general time measurement, input signal pulse width measurement, output waveform generation for signals such as single pulse generation or PWM generation, including dead time insertion.

  • Page 299: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ 16-bit up/down auto-reload counter ▄ 16-bit programmable prescaler that allows division the counter clock frequency by any factor between 1 and 65536 ▄ Up to 4 independent channels for: ●...

  • Page 300: Figure 94. Up-Counting Example

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 CK_PSC CNT_EN CK_CNT CNTR CRR Shadow Register PSCR PSCR Shadow Register PSC_CNT Counter Overflow Update Event 1 Flag Write a new value Software clearing Update the new value Figure 94. Up-counting Example...

  • Page 301: Figure 96. Center-Aligned Counting Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Center-Aligned Counting In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer Module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode.

  • Page 302: Figure 97. Update Event 1 Dependent Repetition Mechanism Example

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Repetition Down-counter Operation The update event 1 is usually generated at each overflow or underflow event occurrence. However, when the repetition operation is active by assigning a non-zero value into the REPR register, the update event is only generated if the REPR counter has reached zero.

  • Page 303: Clock Controller

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Controller The following describes the Timer Module clock controller which determines the internal prescaler counter clock source. ▄ Internal APB clock f CLKIN The default internal clock source is the APB clock f...

  • Page 304: Trigger Controller

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Trigger Controller The trigger controller is used to select the trigger source and setup the trigger level and edge trigger conditions. For the internal trigger input (ITIx), it can be selected by the Trigger Selection bits, TRSEL, in the TRCFR register.

  • Page 305: Slave Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Slave Controller The MCTM can be synchronised with an internal/external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which are selected by the SMSEL field in the MDCFR register.

  • Page 306: Figure 102. Mctm In Pause Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pause Mode In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level.

  • Page 307: Master Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master Controller The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining. When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will generate a Master Trigger Output (MTO) signal which can reset, restart, stop the Slave counter or be a clock source of the Slave Counter.

  • Page 308: Channel Controller

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Controller The MCTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.

  • Page 309: Input Stage

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Pulse Width Measurement The input capture mode can be also used for pulse width measurement from signals on the MT_ CHx pins, TIx. The following example shows how to configure the MCTM when operated in the input capture mode to measure the high pulse width and the input period on the MT_CH0 pin using channel 0 and channel 1.

  • Page 310: Figure 109. Channel 0 And Channel 1 Input Stages

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 TRCED TI0SRC Edge CLKIN Detection MT_CH0 TI0BED TI0XOR MT_CH1 Edge MT_CH2 Detection CH0CCS CLKIN Edge TI0S0 TI0S0ED TI0FP TI0FN Detection Filter sampling CH0PSC CH0PRESCALER CH0P CH0CAP Event TI0F Edge TI1S0 TI1S0ED CH0PSC...

  • Page 311: Output Stage

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 No Filtered Digital Filter (N=2) Filtered SYSTEM sampling Figure 111. TI0 Digital Filter Diagram with N = 2 Output Stage The MCTM supports complementary outputs for channels 0, 1 and 2 with dead time insertion. The MCTM channel 3 output function is almost the same as that of GPTM channel 3 except for the break function.

  • Page 312: Table 30. Compare Match Output Setup

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Output Reference Signal When the MCTM is used in the compare match output mode, the CHxOREF signal (Channel x Output Reference signal) is defined by the CHxOM bit setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register.

  • Page 313: Figure 114. Toggle Mode Channel Output Reference Signal - Chxpre = 1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value CHxOM = 0x3, CHxPRE = 1 (Output toggle, preload enable) CHxCCR (New value 2) CHxCCR (New value 3) CHxCCR (New value 1) CHxCCR Time Update CHxCCR value CHxOREF UEV1 (Update Event 1) Figure 114.

  • Page 314: Figure 116. Pwm Mode Channel Output Reference Signal And Counter In Down-Counting Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Counter Value Counter Value CHxCCR CHxCCR CHxOM = 0x6 100% CHxOREF CHxOREF CHxCCIF CHxCCIF CHxOM = 0x7 CHxOREF CHxOREF Figure 116. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode...

  • Page 315: Figure 118. Dead-Time Insertion Performed For Complementary Outputs

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Dead Time Generator An 8-bit dead time generator function is included for channels 0 ~ 2. The dead time insertion is enabled by setting both the CHxE and CHxNE bits. The relationship between the CHxO and CHxNO signals with respect to the CHxOREF signal is as follows: ▄...

  • Page 316: Figure 119. Mctm Break Signal Bolck Diagram

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Break Function The MCTM includes break function and one input signal for MCTM break. The MT_BRK is default function and from the external MT_BRK pin. The detailed block diagram is shown as below.

  • Page 317: Figure 121. Channel 3 Output With A Break Event Occurrence

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 When using the break function, the channel output enable signals and output levels are changed depending on several control bits which include the CHMOE, CHOSSI, CHOSSR, CHxOIS and CHxOISN bits. Once a break event occurs, the output enable bit CHMOE will be cleared asynchronously.

  • Page 318: Figure 122. Channel 0 ~2 Complementary Outputs With A Break Event Occurrence

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 The accompanying diagram shows that the complementary output states when a break event occurs where the complementary outputs are enabled by setting both the CHxE and CHxNE bits to 1. Break event CHMOE...

  • Page 319: Figure 123. Channel 0 ~2 Only One Output Enabled When Break Event Occurs

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 The accompanying diagram shows the output states in the case of the output being enabled by setting the CHxE bit to 1 and the complementary output being disabled by clearing the CHxNE to 0 when a break event occurs.

  • Page 320: Figure 124. Hardware Protection When Both Chxo And Chxno Are In Active Condition

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 The CHxO and CHxNO complementary outputs should not be set to an active level at the same time. The hardware will protect the MCTM circuitry to force only one channel output to be in the active state.

  • Page 321: Table 35. Output Control Bits For Complementary Output With A Break Event Occurrence

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Complementary Output with Break Function The Channel complementary outputs, CHxO and CHxNO, are enabled by a combination of the CHxE, CHxNE, CHMOE, CHOSSR, CHOSSI control bits. Table 35. Output Control Bits for Complementary Output with a Break Event Occurrence...

  • Page 322: Update Management

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Update Management The update events are categorised into two different types which are the update event 1, UEV1, and update event 2, UEV2. The update event 1 is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers.

  • Page 323: Figure 126. Chxe, Chxne And Chxom Updated By Update Event 2

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Update Event 2 The CHxE, CHxNE, CHxOM control bits for the complementary outputs can be preloaded by setting the COMPRE bit in the CTR register. Here the shadow bits of the CHxE, CHxNE, and CHxOM bits will be updated when an update event 2 occurs.

  • Page 324: Single Pulse Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software.

  • Page 325: Figure 129. Immediate Active Mode Minimum Delay

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, users can set the CHxIMAE bit in each CHxOCFR register.

  • Page 326: Figure 130. Asymmetric Pwm Mode Versus Center-Aligned Counting Mode

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Asymmetric PWM Mode Asymmetric PWM mode allows two center-aligned PWM signals to be genetated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.

  • Page 327: Timer Interconnection

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the master mode while configuring another timer to be in the slave mode. The following figures present several examples of trigger selection for the master and slave modes.

  • Page 328: Figure 132. Triggering Gptm With Mctm Update Event 1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Using One Timer to Trigger Another Timer to Start Counting ▄ Configure MCTM to operate in the master mode and to send its Update Event UEV as the trigger output (MMSEL = 0x2).

  • Page 329: Figure 133. Figure 41 Trigger Mctm And Gptm With The Mctm Ch0 Input

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Starting Two Timers Synchronously in Response to an External Trigger ▄ Configure MCTM to operate in the master mode to send its enable signal as a trigger output (MMSEL = 0x1). ▄...

  • Page 330: Figure 134. Ch1Xor Input As Hall Sensor Interface

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Using One Timer as a Hall Sensor Interface to Trigger Another Timer with Update Event 2 GPTM: ▄ Configure channel 0 to choose an input XOR function (TI0SRC = 1) ▄ Configure channel 0 to be in the input capture mode and TRCED as capture source (CH0CCS = 0x3) and Enable channel 0 (CH0E = 1) ▄...

  • Page 331: Trigger Adc Start

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Trigger ADC Start To interconnect to the Analog-to-Digital Converter, the MCTM can output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as an Analog-to-Digital Converter input trigger signal.

  • Page 332: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Offset Description Reset Value CHBRKCFR 0x06C Channel Break Configuration Register 0x0000_0000 CHBRKCTR 0x070 Channel Break Control Register 0x0000_0002 DICTR 0x074 Timer Interrupt Control Register 0x0000_0000 EVGR 0x078 Timer Event Generator Register...
  • Page 333 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] CMSEL Counter Mode Selection 00: Edge-aligned counting mode. Normal up-counting and down-counting available for this mode. Counting direction is defined by the DIR bit. 01: Center-aligned counting mode 1. The counter counts up and down alternatively.

  • Page 334: Timer Mode Configuration Register - Mdcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Mode Configuration Register – MDCFR This register specifies the MCTM master and slave mode selection and single pulse mode. Offset: 0x004 Reset value: 0x0000_0000 Reserved SPMSET Type/Reset Reserved MMSEL Type/Reset 0 RW...
  • Page 335 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [18:16] MMSEL Master Mode Selection Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer. The Channel 3 Output reference signal named CH3OREF is used as the trigger output.
  • Page 336 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [10:8] SMSEL Slave Mode Selection SMSEL [2:0] Mode Descriptions Disable mode The prescaler is clocked directly by the internal clock. Reserved Reserved Reserved The counter value restarts from 0 or the CRR shadow...

  • Page 337: Timer Trigger Configuration Register - Trcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Trigger Configuration Register – TRCFR This register specifies the trigger source selection of MCTM. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved TRSEL Type/Reset 0 RW 0 RW...

  • Page 338: Timer Control Register - Ctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Control Register – CTR This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Capture/compare control bit. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...

  • Page 339: Channel 0 Input Configuration Register - Ch0Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Input Configuration Register – CH0ICFR This register specifies the channel 0 input mode configuration. Offset: 0x020 Reset value: 0x0000_0000 TI0SRC Reserved Type/Reset Reserved CH0PSC CH0CCS Type/Reset 0 RW 0 RW...

  • Page 340: Channel 1 Input Configuration Register - Ch1Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [3:0] TI0F Channel 0 Input Source TI0 Filter Setting These bits define the frequency divided ratio used to sample the TI0 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
  • Page 341 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] CH1CCS Channel 1 Capture/Compare Selection 00: Channel 1 is configured as an output 01: Channel 1 is configured as an input derived from the TI1 signal 10: Channel 1 is configured as an input derived from the TI0 signal...

  • Page 342: Channel 2 Input Configuration Register - Ch2Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Input Configuration Register – CH2ICFR This register specifies the channel 2 input mode configuration. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved CH2PSC CH2CCS Type/Reset 0 RW 0 RW 0 RW...

  • Page 343: Channel 3 Input Configuration Register - Ch3Icfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [3:0] TI2F Channel 2 Input Source TI2 Filter Setting These bits define the frequency divide ratio used to sample the TI2 signal. The Digital filter in the MCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
  • Page 344 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] CH3CCS Channel 3 Capture/Compare Selection 00: Channel 3 is configured as an output 01: Channel 3 is configured as an input derived from the TI3 signal 10: Channel 3 is configured as an input derived from the TI2 signal...

  • Page 345: Channel 0 Output Configuration Register - Ch0Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Output Configuration Register – CH0OCFR This register specifies the channel 0 output mode configuration. Offset: 0x040 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH0OM[3] Type/Reset Reserved CH0IMAE CH0PRE Reserved...
  • Page 346 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH0OM[3:0] Channel 0 Output Mode Setting These bits define the functional types of the output reference signal CH0OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 347: Channel 1 Output Configuration Register - Ch1Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Output Configuration Register – CH1OCFR This register specifies the channel 1 output mode configuration. Offset: 0x044 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH1OM[3] Type/Reset Reserved CH1IMAE CH1PRE Reserved...
  • Page 348 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH1OM[3:0] Channel 1 Output Mode Setting These bits define the functional types of the output reference signal CH1OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 349: Channel 2 Output Configuration Register - Ch2Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Output Configuration Register – CH2OCFR This register specifies the channel 2 output mode configuration. Offset: 0x048 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH2OM[3] Type/Reset Reserved CH2IMAE CH2PRE Reserved...
  • Page 350 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH2OM[3:0] Channel 2 Output Mode Setting These bits define the functional types of the output reference signal CH2OREF. 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 351: Channel 3 Output Configuration Register - Ch3Ocfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Output Configuration Register – CH3OCFR This register specifies the channel 3 output mode configuration. Offset: 0x04C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved CH3OM[3] Type/Reset Reserved CH3IMAE CH3PRE Reserved...
  • Page 352 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting These bits define the functional types of the output reference signal CH3OREF 0000: No Change 0001: Output 0 on compare match 0010: Output 1 on compare match 0011: Output toggles on compare match 0100: Force inactive –...

  • Page 353: Channel Control Register - Chctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Control Register – CHCTR This register contains the channel capture input or compare output function enable control bits. Offset: 0x050 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3E...
  • Page 354 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH1NE Channel 1 Capture/Compare Complementary Enable 0: Off – Channel 1 complementary output CH1NO is not active. The CH1NO level is then determined by the condition of the CHMOE, CHOSSI, CHOSSR, CH1OIS, CH1OISN and CH1E bits.

  • Page 355: Channel Polarity Configuration Register - Chpolr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel Polarity Configuration Register – CHPOLR This register contains the channel capture input or compare output polarity control. Offset: 0x054 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved CH3P CH2NP...

  • Page 356: Channel Break Configuration Register - Chbrkcfr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH0P Channel 0 Capture/Compare Polarity - When Channel 0 is configured as an input (CH0CCS = 0x1 / 0x2 / 0x3) 0: capture event occurs on a Channel 0 rising edge...

  • Page 357: Channel Break Control Register - Chbrkctr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH0OISN MT_CH0NO Output Idle State 0: Channel 0 complementary output CH1NO = 0 after a dead time when CHMOE = 0 1: Channel 0 complementary output CH1NO = 1 after a dead time when...
  • Page 358 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17:16] LOCKLV Lock Level Setting These bits offer write protection against software errors. The bits can be written only once after a reset. 00: LOCK OFF, Register write protected function is disabled...

  • Page 359: Timer Interrupt Control Register - Dictr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interrupt Control Register – DICTR This register contains the timer interrupt enable control bits. Offset: 0x074 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKIE TEVIE UEV2IE UEV1IE Type/Reset 0 RW...

  • Page 360: Timer Event Generator Register - Evgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Event Generator Register – EVGR This register contains the software event generation bits. Offset: 0x078 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKG TEVG UEV2G UEV1G Type/Reset 0 WO 0 WO...
  • Page 361 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH3CCG Channel 3 Capture/Compare Generation A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically. 0: No action 1: Capture/compare event is generated on channel 3 If Channel 3 is configured as an input, the counter value is captured into the CH3CCR register and then the CH3CCIF bit is set.

  • Page 362: Timer Interrupt Status Register - Intsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Interrupt Status Register – INTSR This register stores the timer interrupt status. Offset: 0x07C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved BRKIF TEVIF UEV2IF UEV1IF Type/Reset 0 RW 0 RW...
  • Page 363 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH2OCF Channel 2 Over-capture Flag This flag is set by hardware and cleared by software. 0: No over-capture event is detected 1: Capture event occurs again when the CH2CCIF bit is already set and it is not...

  • Page 364: Timer Counter Register - Cntr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions CH0CCIF Channel 0 Capture/Compare Interrupt Flag - Channel 0 is configured as an output 0: No match event occurs 1: The contents of the counter CNTR have matched the content of the CH0CCR...

  • Page 365: Timer Prescaler Register - Pscr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Prescaler Register – PSCR This register specifies the timer prescaler value to generate the counter clock. Offset: 0x084 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PSCV Type/Reset 0 RW 0 RW...

  • Page 366: Timer Counter Reload Register - Crr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Timer Counter Reload Register – CRR This register specifies the timer counter reload value. Offset: 0x088 Reset value: 0x0000_FFFF Reserved Type/Reset Reserved Type/Reset Type/Reset 1 RW 1 RW 1 RW 1 RW...

  • Page 367: Channel 0 Capture/Compare Register - Ch0Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Capture/Compare Register – CH0CCR This register specifies the timer channel 0 capture/compare value. Offset: 0x090 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 368: Channel 1 Capture/Compare Register - Ch1Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 1 Capture/Compare Register – CH1CCR This register specifies the timer channel 1 capture/compare value. Offset: 0x094 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH1CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 369: Channel 2 Capture/Compare Register - Ch2Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Capture/Compare Register – CH2CCR This register specifies the timer channel 2 capture/compare value. Offset: 0x098 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 370: Channel 3 Capture/Compare Register - Ch3Ccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 3 Capture/Compare Register – CH3CCR This register specifies the timer channel 3 capture/compare value. Offset: 0x09C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH3CCV Type/Reset 0 RW 0 RW 0 RW...

  • Page 371: Channel 0 Asymmetric Compare Register - Ch0Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 0 Asymmetric Compare Register – CH0ACR This register specifies the timer channel 0 asymmetric compare value. Offset: 0x0A0 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH0ACV Type/Reset 0 RW 0 RW...

  • Page 372: Channel 2 Asymmetric Compare Register - Ch2Acr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Channel 2 Asymmetric Compare Register – CH2ACR This register specifies the timer channel 2 asymmetric compare value. Offset: 0x0A8 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset CH2ACV Type/Reset 0 RW 0 RW...

  • Page 373: Real Time Clock (Rtc)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Real Time Clock (RTC) Introduction The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control register, a prescaler, a compare register and a status register. The RTC circuits are located in the Domain, as shown shaded in the accompanying figure.

  • Page 374: Functional Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Descriptions RTC Related Register Reset The RTC registers can only be reset by either a V Domain power on reset, POR15, or by a DD15 PWRCU software reset by setting the PWCURST bit in the PWRCR register. Other reset events have no effect to clear the RTC registers.

  • Page 375: Rtcout Output Pin Configuration

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 oscillators, the LDO and the CPU core if the corresponding wakeup enable bit CSECWEN is set. When the RTC counter overflows or a compare match event occurs, it will generate an interrupt or a wake up event determined by the corresponding interrupt or wakeup enable control bits, OVIEN / OVWEN or CMIEN / CMWEN bits, in the RTCIWEN register.

  • Page 376: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V power domain. DD15 Table 41. RTC Register Map...

  • Page 377: Rtc Compare Register - Rtccmp

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 RTC Compare Register – RTCCMP This register defines a specific value to be compared with the RTC counter value. Offset: 0x004 Reset value: 0x0000_0000 (Reset by V Power Domain reset only) DD15...

  • Page 378: Rtc Control Register - Rtccr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 RTC Control Register – RTCCR This register specifies a range of RTC circuitry control bits. Offset: 0x008 Reset value: 0x0000_0F00 (Reset by V Power Domain reset only) DD15 Reserved Type/Reset Reserved ROLF...
  • Page 379 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [11:8] RPRE RTC Clock Prescaler Select CK_SECOND = CK_RTC / 2 RPRE 0000: CK_SECOND = CK_RTC / 2 0001: CK_SECOND = CK_RTC / 2 0010: CK_SECOND = CK_RTC / 2 …...

  • Page 380: Rtc Status Register - Rtcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 RTC Status Register – RTCSR This register stores the counter flags. Offset: 0x00C Reset value: 0x0000_0000 (Reset by V Power Domain reset and RTCEN bit change from 1 to 0) DD15 Reserved...

  • Page 381: Rtc Interrupt And Wakeup Enable Register - Rtciwen

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 RTC Interrupt and Wakeup Enable Register – RTCIWEN This register contains the interrupt and wakeup enable bits. Offset: 0x010 Reset value: 0x0000_0000 (Reset by V Power Domain reset only) DD15 Reserved Type/Reset...

  • Page 382: Watchdog Timer (Wdt)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer (WDT) Introduction The Watchdog timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog timer can be operated in a reset mode. The Watchdog timer will generate a reset when the counter counts down to a zero value.

  • Page 383: Functional Description

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Description The Watchdog timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value.

  • Page 384: Figure 137. Watchdog Timer Behavior

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 The Watchdog timer should be used in the following manners: ▄ Set the Watchdog timer reload value (WDTV) and reset in the WDTMR0 register. ▄ Set the Watchdog timer delta value (WDTD) and prescaler in the WDTMR1 register.

  • Page 385: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the Watchdog Timer registers and reset values. Table 42. Watchdog Timer Register Map Register Offset Description Reset Value WDTCR 0x000 Watchdog Timer Control Register 0x0000_0000 WDTMR0...

  • Page 386: Watchdog Timer Mode Register 0 - Wdtmr0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer Mode Register 0 – WDTMR0 This register specifies the Watchdog timer counter reload value and reset enable control. Offset: 0x004 Reset value: 0x0000_0FFF Reserved Type/Reset Reserved WDTEN Type/Reset WDTSHLT WDTRSTEN Reserved...

  • Page 387: Watchdog Timer Mode Register 1 - Wdtmr1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer Mode Register 1 – WDTMR1 This register specifies the Watchdog delta value and the prescaler selection. Offset: 0x008 Reset value: 0x0000_5FFF Reserved Type/Reset Reserved Type/Reset Reserved WPSC WDTD Type/Reset 1 RW...

  • Page 388: Watchdog Timer Status Register - Wdtsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer Status Register – WDTSR This register specifies the Watchdog timer status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTERR WDTUF Type/Reset 0 WC Bits Field...

  • Page 389: Watchdog Timer Protection Register - Wdtpr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer Protection Register – WDTPR This register specifies the Watchdog timer protect key configuration. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset PROTECT Type/Reset 0 RW 0 RW 0 RW...

  • Page 390: Watchdog Timer Clock Selection Register - Wdtcsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Watchdog Timer Clock Selection Register – WDTCSR This register specifies the Watchdog timer clock source selection and lock configuration. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved WDTLOCK...

  • Page 391: Inter-Integrated Circuit

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Inter-Integrated Circuit (I Introduction The I C Module is an internal circuit allowing communication with an external I C interface which is an industry standard two-wire serial interface used for connection to external hardware. These two serial lines are known as a serial data line, SDA, and a serial clock line, SCL.

  • Page 392: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Two-wire I C serial interface ● Serial data line (SDA) and serial clock (SCL) ▄ Multiple speed modes ● Standard mode – 100 kHz ● Fast mode – 400 kHz ●...

  • Page 393: Data Validity

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 STOP Condition START Condition Figure 139. START and STOP Condition Data Validity The data on the SDA line must be stable during the high period of the SCL clock. The SDA data state can only be changed when the clock signal on the SCL line is in a low state.

  • Page 394: Addressing Format

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Addressing Format The I C interface starts to transfer data after the master device has sent the address to confirm the targeted slave device. The address frame is sent just after the START signal by the master device.

  • Page 395: Figure 142. 10-Bit Addressing Write Transmit Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 10-bit Address Format In order to prevent address clashes, due to the limited range of the 7-bit addresses, a new 10-bit address scheme has been introduced. This enhancement can be mixed with the 7-bit addressing mode which increases the available address range about ten times.

  • Page 396: Data Transfer And Acknowledge

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Data Transfer and Acknowledge Once the slave device address has been matched, the data can be transmitted to or received from the slave device according to the transfer direction specified by the R/W bit. Each byte is followed by an acknowledge bit on the 9 SCL clock.

  • Page 397: Clock Synchronization

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Clock Synchronization Only one master device can generate the SCL clock under normal operation. However when there is more than one master trying to generate the SCL clock, the clock should be synchronized so that the data output can be compared.

  • Page 398: General Call Addressing

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 General Call Addressing The general call addressing function can be used to address all the devices connected to the I bus. The master device can activate the general call function by writing a value “00” into the TAR field and setting the RWD bit to 0 in the I2CTAR register on the addressing frame.

  • Page 399: Figure 147. Master Transmitter Timing Diagram

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master Transmitter Mode Start Condition Users write the target slave device address and communication direction into the I2CTAR register after setting the I2CEN bit in the I2CCR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs.
  • Page 400 ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Master Receiver Mode Start Condition The target slave device address and communication direction must be written into the I2CTAR register. The STA flag in the I2CSR register is set by hardware after a start condition occurs. In order to send the following address frame, the STA flag must be cleared to 0 if it has been set to 1.

  • Page 401: Figure 148. Master Receiver Timing Diagram

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Close / Continue Transmission The master device needs to reset the AA bit in the I2CCR register to send a NACK signal to the slave device before the last data byte transfer has been completed. After the last data byte has been received from the slave device, the master device will hold the SCL line at a logic low state following after a NACK signal sent by the master device to the slave device.

  • Page 402: Figure 149. Slave Transmitter Timing Diagram

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Slave Transmitter Mode Address Frame In the 7-bit addressing mode, the ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. In the 10-bit addressing mode, the ADRS bit is set for the first time when the first header byte and the second address byte are both matched.

  • Page 403: Figure 150. Slave Receiver Timing Diagram

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Slave Receiver Mode Address Frame The ADRS bit in the I2CSR register is set after the slave device receives the calling address which matches with the slave device address. After the ADRS bit has been set to 1, it must be cleared to 0 to continue the data transfer process.

  • Page 404: Conditions Of Holding Scl Line

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Conditions of Holding SCL Line The following conditions will cause the SCL line to be held at a logic low state by hardware resulting in all the I C transfers being stopped. Data transfer will be continued after the creating conditions are eliminated.

  • Page 405: I 2 C Timeout Function

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Timeout Function In order to reduce the occurrence of I C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I C bus clock source is not received for a certain timeout period, then a corresponding I C timeout flag will be asserted.

  • Page 406: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions C Control Register – I2CCR This register specifies the corresponding I C function enable control. Offset: 0x000 (0) Reset value: 0x0000_2000 Reserved Type/Reset Reserved Type/Reset SEQFILTER ENTOUT Reserved COMBFILTEREN Type/Reset...

  • Page 407: I 2 C Interrupt Enable Register - I2Cier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions GCEN General Call Enable 0: General call is disabled 1: General call is enabled When the device receives the calling address with a value of 0x00 and if both...
  • Page 408 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [16] RXDNEIE Data Register Not Empty Interrupt Enable Bit in Received Mode 0: Interrupt is disabled 1: Interrupt is enabled When the I2CEN bit in the I2CCR register is cleared to 0, this bit is cleared to 0 by hardware.

  • Page 409: I 2 C Address Register - I2Caddr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Address Register – I2CADDR This register specifies the I C device address. Offset: 0x008 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved ADDR Type/Reset 0 RW ADDR Type/Reset 0 RW 0 RW...

  • Page 410: I 2 C Status Register - I2Csr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Status Register – I2CSR This register contains the I C operation status. Offset: 0x00C Reset value: 0x0000_0000 Reserved Type/Reset Reserved TXNRX MASTER BUSBUSY RXBF TXDE RXDNE Type/Reset 0 RO 0 RO...
  • Page 411 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [17] TXDE Data Register Empty Using in Transmitter Mode 0: Data register I2CDR is not empty 1: Data register I2CDR is empty This bit is set when the I2CDR register is empty in the Transmitter mode. Note that the TXDE bit will be set after the address frame is being transmitted to inform that the data to be transmitted should be loaded into the I2CDR register.
  • Page 412 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions ADRS Address Transmit (master mode) / Address Receive (slave mode) Flag Address Sent in Master Mode 0: Address frame has not been transmitted 1: Address frame has been transmitted For the 7-bit addressing mode, this bit is set after the master device receives the address frame acknowledge bit sent from the slave device.

  • Page 413: C Scl High Period Generation Register - I2Cshpgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C SCL High Period Generation Register – I2CSHPGR This register specifies the I C SCL clock high period interval. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SHPG Type/Reset 0 RW...

  • Page 414: I 2 C Scl Low Period Generation Register - I2Cslpgr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C SCL Low Period Generation Register – I2CSLPGR This register specifies the I C SCL clock low period interval. Offset: 0x014 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SLPG Type/Reset 0 RW...

  • Page 415: C Data Register - I2Cdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Data Register – I2CDR This register specifies the data to be transmitted or received by the I C module. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset DATA...

  • Page 416: I 2 C Target Register - I2Ctar

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Target Register – I2CTAR This register specifies the target device address to be communicated. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW Type/Reset 0 RW...

  • Page 417: I 2 C Address Mask Register - I2Caddmr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Address Mask Register – I2CADDMR This register specifies which bit of the I C address is masked and not compared with corresponding bit of the received address frame. Offset: 0x020 Reset value: 0x0000_0000...

  • Page 418: I 2 C Address Snoop Register - I2Caddsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Address Snoop Register – I2CADDSR This register is used to indicate the address frame value appeared on the I C bus. Offset: 0x024 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...

  • Page 419: I 2 C Timeout Register - I2Ctout

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 C Timeout Register – I2CTOUT This register specifies the I C Timeout counter preload value and clock prescaler ratio. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset 0 RW 0 RW...

  • Page 420: Serial Peripheral Interface (Spi)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Serial Peripheral Interface (SPI) Introduction The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive functions in both master or slave mode. The SPI interface uses 4 pins, among which are serial data input and output lines MISO and MOSI, the clock line SCK, and the slave select line SEL.

  • Page 421: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Master or slave mode ▄ Master mode speed up to f PCLK ▄ Slave mode speed up to f PCLK ▄ Programmable data frame length up to 16 bits ▄...

  • Page 422: Spi Serial Frame Format

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI Serial Frame Format The SPI interface format is based on the Clock Polarity, CPOL, and the Clock Phase, CPHA, configurations. ▄ Clock Polarity Bit – CPOL When the Clock Polarity bit is cleared to 0, the SCK line idle state is LOW. When the Clock Polarity bit is set to 1, the SCK line idle state is HIGH.

  • Page 423: Figure 154. Spi Continuous Data Transfer Timing Diagram - Cpol = 0, Cpha = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 154 shows the continuous data transfer timing diagram of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO...

  • Page 424: Figure 156. Spi Continuous Transfer Timing Diagram - Cpol = 0, Cpha = 1

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 156 shows the continuous data transfer diagram timing. Note that the SEL signal must remain active until the last data transfer has completed. SEL (SELAP=0) SEL (SELAP=1) MOSI/MISO Data1 Data2 Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1...

  • Page 425: Figure 158. Spi Continuous Transfer Timing Diagram - Cpol = 1, Cpha = 0

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Figure 158 shows the continuous data transfer timing of this format. Note that the SEL signal must change to an inactive level between each data frame. SEL (SELAP=0) SEL (SELAP=1) ½ SCK ½...

  • Page 426: Status Flags

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Status Flags TX Buffer Empty – TXBE This TXBE flag is set when the TX buffer is empty in the non-FIFO mode or when the TX FIFO data length is equal to or less than the TX FIFO threshold level as defined by the TXFTLS field in the SPIFCR register in the FIFO mode.

  • Page 427: Table 47. Spi Mode Fault Trigger Conditions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 MOSI MOSI Master Master MISO MISO I/O 0 I/O 0 I/O 1 I/O 1 I/O 2 I/O 2 MOSI Slave MISO MOSI Slave MISO Figure 161. SPI Multi-Master Slave Environment Table 47. SPI Mode Fault Trigger Conditions...

  • Page 428: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Write Collision – WC The following conditions will assert the Write Collision Flag. ▄ The FIFOEN bit in the SPIFCR register is cleared The write collision flag is asserted when new data is written into the SPIDR register while both the TX buffer and the shift register are already full.

  • Page 429: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions SPI Control Register 0 – SPICR0 This register specifies the SEL control and the SPI enable bits. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset SELHT GUADT Type/Reset 0 RW...
  • Page 430 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions SSELC Software Slave Select Control 0: Set the SEL output to an inactive state 1: Set the SEL output to an active state The application software can setup the SEL output to an active or inactive state by configuring the SSELC bit.

  • Page 431: Spi Control Register 1 - Spicr1

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI Control Register 1 – SPICR1 This register specifies the SPI parameters including the data length, the transfer format, the SEL active polarity / mode, the LSB / MSB control and the master / slave mode.

  • Page 432: Spi Interrupt Enable Register - Spiier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [3:0] Data Frame Length Selects the data transfer frame from 1 bit to 16 bits. 0x1: 1 bit 0x2: 2 bits … 0xF: 15 bits 0x0: 16 bits SPI Interrupt Enable Register – SPIIER This register contains the corresponding SPI interrupt enable control bit.

  • Page 433: Spi Clock Prescaler Register - Spicpr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions RXBNEIEN RX Buffer Not Empty Interrupt Enable 0: Disable 1: Enable Generates an interrupt request when the RXBNE flag is set and when RXBNEIEN is set. In the FIFO mode, the interrupt request being generated depends upon the RX FIFO trigger level setting.

  • Page 434: Spi Data Register - Spidr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI Data Register – SPIDR This register stores the SPI received or transmitted Data. Offset: 0x010 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW 0 RW 0 RW...

  • Page 435: Spi Status Register - Spisr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI Status Register – SPISR This register contains the relevant SPI status. Offset: 0x014 Reset value: 0x0000_0003 Reserved Type/Reset Reserved Type/Reset Reserved BUSY Type/Reset RXBNE TXBE Type/Reset 0 WC 0 WC 0 WC...
  • Page 436 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions Write Collision flag 0: No write collision 1: Write collision has occurred This bit is set by hardware and cleared by writing 1. RXBNE Receive Buffer Not Empty flag...

  • Page 437: Spi Fifo Control Register - Spifcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI FIFO Control Register – SPIFCR This register contains the related SPI FIFO control including the FIFO enable control and the FIFO trigger level selections. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset...

  • Page 438: Spi Fifo Status Register - Spifsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI FIFO Status Register – SPIFSR This register contains the relevant SPI FIFO status. Offset: 0x01C Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset RXFS TXFS Type/Reset 0 RO 0 RO...

  • Page 439: Spi Fifo Time Out Counter Register - Spiftocr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 SPI FIFO Time Out Counter Register – SPIFTOCR This register stores the SPI RX FIFO timeout counter value. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW 0 RW...

  • Page 440: Universal Synchronous Asynchronous Receiver Transmitter (Usart)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Universal Synchronous Asynchronous Receiver Transmitter (USART) Introduction The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.

  • Page 441: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Supports both asynchronous and clocked synchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate clock frequency up to (f /16) MHz for asynchronous mode and PCLK...

  • Page 442: Baud Rate Generation

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 7-Bit Data Format (WLS[1:0]=b00, PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Stop Bit 8-Bit Data Format (WLS[1:0]=b01, PBE=0) Next Start Start Bit Bit0 Bit1 Bit2 Bit3 Bit4...

  • Page 443: Hardware Flow Control

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 50. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz Baud Rate CK_USART = 20 MHz Kbps Actual Deviation Error Rate 8333 0.00% 2083 0.02% 19.2 19.2 1042 -0.03% 57.6 57.6...

  • Page 444: Irda

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 RTS Flow Control In the RTS flow control, the USART RTS pin is active with a logic low state when the receive data register is empty. It means that the receiver is ready to receive a new data. When the RX FIFO reaches the trigger level which is specified by configuring the RXTL field in the USRFCR register, the USART RTS pin is inactive with a logic high state.

  • Page 445: Figure 168. Irda Modulation And Demodulation

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Data Frame STOP START TX_Data IrDA TX Modulation Signal bit width 3/16 bit width IrDA RX Demodulation Signal Data Frame STOP START RX_Data Figure 168. IrDA Modulation and Demodulation The IrDA mode provides two operation modes, one is the normal mode and the other is the low- power mode.

  • Page 446: Rs485 Mode

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 = 3 × IrDAPSC / CK_USART IrDA_L Note: T is the transmitted pulse width in the low-power mode. IrDA_L The IrDAPSC filed is the IrDA prescaler value in the IrDA Control Register IrDACR.

  • Page 447: Figure 170. Rs485 Interface And Waveform

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 RS485 Transceiver Differential USART TG = 4 Reference Divisor Clock Stop D6 D7 Parity Start D1 D2 D3 D4 D5 TXENP = 0 TXENP = 1 Figure 170. RS485 Interface and Waveform RS485 Normal Multi-drop Operation Mode –...

  • Page 448: Synchronous Master Mode

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 RS485 Auto Address Detection Operation Mode – AAD Except in the Normal Multi-drop Operation Mode, the RS485 mode can operate in the Auto Address Detection Operation Mode, AAD, when it is configured as an addressable slave. This mode is enabled by setting the RSAAD filed to 1 in the RS485CR register.

  • Page 449: Figure 172. Figure 11. 8-Bit Format Usart Synchronous Waveform

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 (CPS = 1, WLS[1:0] = b01, PBE = 0) Clock (CPO = 0) Clock (CPO = 1) USART TX (From Start Stop Master to Slave) USART RX (From Slave to Master) (CPS = 1, WLS[1:0] = b00, PBE = 1)

  • Page 450: Interrupts And Status

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Interrupts and Status The USART can generate interrupts when the following event occurs and corresponding interrupt enable bits are set: ▄ Receive FIFO time-out interrupt: An interrupt will be generated when the USART receive FIFO is not empty and does not receive a new data package during the specified time-out interval.

  • Page 451: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions USART Data Register – USRDR The register is used to access the USART transmitted and received FIFO data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset...

  • Page 452: Usart Control Register - Usrcr

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Control Register – USRCR The register specifies the serial parameters such as data length, parity and stop bit for the USART. It also contains the USART enable control bits together with the USART mode and data transfer mode selections.
  • Page 453 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions [10] Number of “STOP bit” 0: One “STOP bit” is generated in the transmitted data 1: Two “STOP bit” is generated when 8-bit and 9-bit word length is selected...

  • Page 454: Usart Fifo Control Register - Usrfcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART FIFO Control Register – USRFCR This register specifies the USART FIFO control and configurations including threshold level and reset function together with the USART FIFO status. Offset: 0x008 Reset value: 0x0000_0000...

  • Page 455: Usart Interrupt Enable Register - Usrier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions TX FIFO Reset Setting this bit will generate a reset pulse to reset the TX FIFO which will empty the TX FIFO, i.e., the TX pointer will be reset to 0 after a reset signal. This bit returns to 0 automatically after the reset pulse is generated.
  • Page 456 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions FEIE Framing Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt If this bit is set, an interrupt will be generated when the FEI bit is set in the URSIFR register.

  • Page 457: Usart Status & Interrupt Flag Register - Usrsifr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Status & Interrupt Flag Register – USRSIFR This register contains the corresponding USART status. Offset: 0x010 Reset value: 0x0000_0180 Reserved Type/Reset Reserved Type/Reset Reserved CTSS CTSC RSADD Type/Reset 0 WC 0 WC...
  • Page 458 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions RXTOF Receive FIFO Time-Out Flag 0: RX FIFO Time-Out does not occur 1: RX FIFO Time-Out occurs The RXTOF bit will be set if the receive FIFO is not empty and no activities have occurred in the receive FIFO during the time-out duration specified by the RXTOC field.

  • Page 459: Usart Timing Parameter Register - Usrtpr

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Timing Parameter Register – USRTPR This register contains the USART timing parameters including the transmitter time guard parameters and the receive FIFO time-out value together with the RX FIFO time-out function enable control.

  • Page 460: Usart Irda Control Register - Irdacr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART IrDA Control Register – IrDACR This register is used to control the IrDA mode of USART. Offset: 0x018 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset IrDAPSC Type/Reset 0 RW 0 RW...

  • Page 461: Usart Rs485 Control Register - Rs485Cr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions IrDAEN IrDA Enable control 0: Disable IrDA mode 1: Enable IrDA mode USART RS485 Control Register – RS485CR This register is used to control the RS485 mode of USART.

  • Page 462: Usart Synchronous Control Register - Syncr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Synchronous Control Register – SYNCR This register is used to control the USART synchronous mode. Offset: 0x020 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Reserved CLKEN Type/Reset 0 RW...

  • Page 463: Usart Divider Latch Register - Usrdlr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Divider Latch Register – USRDLR The register is used to determine the USART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...

  • Page 464: Usart Test Register - Usrtstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 USART Test Register – USRTSTR This register controls the USART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...

  • Page 465: Universal Asynchronous Receiver Transmitter (Uart)

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Universal Asynchronous Receiver Transmitter (UART) Introduction The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data exchange using asynchronous transfer. The UART is used to translate data between parallel and serial interfaces, and is also commonly used for RS232 standard communication.

  • Page 466: Features

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Features ▄ Supports asynchronous serial communication modes ▄ Full Duplex Communication Capability ▄ Programming baud rate clock frequency up to (f /16) MHz PCLK ▄ Fully programmable serial communication functions including: ●...

  • Page 467: Baud Rate Generation

    Cortex ® -M0+ MCU HT32F50231/HT32F50241 Baud Rate Generation The baud rate for the UART receiver and transmitter are both set with the same values. The baud- rate divisor, BRD, has the following relationship with the UART clock which is known as CK_ UART.

  • Page 468: Interrupts And Status

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Table 54. Baud Rate Deviation Error Calculation – CK_UART = 10 MHz Baud Rate CK_UART = 10 MHz Kbps Actual Deviation Error Rate 4167 -0.01% 1042 -0.03% 19.2 19.2 -0.03% 57.6 57.6 -0.22%...

  • Page 469: Register Descriptions

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Descriptions UART Data Register – URDR The register is used to access the UART transmitted and received data. Offset: 0x000 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Type/Reset 0 RW...

  • Page 470: Uart Control Register - Urcr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 UART Control Register – URCR The register specifies the serial parameters such as data length, parity and stop bit for the UART. Offset: 0x004 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved...

  • Page 471: Uart Interrupt Enable Register - Urier

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions URRXEN UART RX Enable 0: Disable 1: Enable URTXEN UART TX Enable 0: Disable 1: Enable TRSM Transfer Mode Selection This bit is used to select the data transfer protocol.

  • Page 472: Uart Status & Interrupt Flag Register - Ursifr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions OEIE Overrun Error Interrupt Enable 0: Disable interrupt 1: Enable interrupt If this bit is set, an interrupt is generated when the overrun error interrupt is enabled and the OEI bit is set in the URSIFR register.
  • Page 473 32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions TXDE Transmit Data Register Empty 0: Transmit data register is not empty 1: Transmit data register is empty The TXDE bit is set by hardware when the content of the transmit data register is transferred to the transmit shift register (TSR).

  • Page 474: Uart Divider Latch Register - Urdlr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 UART Divider Latch Register – URDLR The register is used to determine the UART clock divided ratio to generate the appropriate baud rate. Offset: 0x024 Reset value: 0x0000_0010 Reserved Type/Reset Reserved Type/Reset...

  • Page 475: Uart Test Register - Urtstr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 UART Test Register – URTSTR This register controls the UART debug mode. Offset: 0x028 Reset value: 0x0000_0000 Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset Reserved Type/Reset 0 RW Bits Field Descriptions [1:0] Loopback Test Mode Select...

  • Page 476: Divider (Div)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Divider (DIV) Introduction In order to enhance the MCU performance, a divider is integrated in the devices. The divider can implement the signed or unsigned 32-bit data division operation. An error flag will be generated when the division by zero condition occurs.

  • Page 477: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the DIV registers and reset values. Table 56. DIV Register Map Register Offset Description Reset Value 0x000 Divider Control Register 0x0000_0008 0x004 Dividend Data Register 0x0000_0000...

  • Page 478: Dividend Data Register - Ddr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Dividend Data Register – DDR The register is used to specify the dividend data. Offset: 0x004 Reset value: 0x0000_0000 Type/Reset 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW...

  • Page 479: Quotient Data Register - Qtr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Quotient Data Register – QTR The register is used to store the quotient data. Offset: 0x00C Reset value: 0x0000_0000 Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...

  • Page 480: Cyclic Redundancy Check (Crc)

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Cyclic Redundancy Check (CRC) Introduction The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and is used to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder.

  • Page 481: Functional Descriptions

    ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Functional Descriptions This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomials. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated.

  • Page 482: Register Map

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Register Map The following table shows the CRC registers and reset values. Table 57. CRC Register Map Register Offset Description Reset Value CRCCR 0x000 CRC Control Register 0x0000_0000 CRCSDR 0x004 CRC Seed Register...

  • Page 483: Crc Seed Register - Crcsdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 Bits Field Descriptions DATBIRV Bit Reverse operation on Data 0: Disable 1: Enable [1:0] POLY CRC polynomial 00: CRC-CCITT (0x1021) 01: CRC-16 (0x8005) 1x: CRC-32 (0x04C11DB7) CRC Seed Register – CRCSDR This register is used to specify the CRC seed.

  • Page 484: Crc Checksum Register - Crccsr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 CRC Checksum Register – CRCCSR This register contains the CRC checksum output. Offset: 0x008 Reset value: 0x0000_0000 CHKSUM Type/Reset 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO...

  • Page 485: Crc Data Register - Crcdr

    32-Bit Arm ® Cortex ® -M0+ MCU HT32F50231/HT32F50241 CRC Data Register – CRCDR This register is used to specify the CRC input data. Offset: 0x00C Reset value: 0x0000_0000 CRCDATA Type/Reset 0 WO 0 WO 0 WO 0 WO 0 WO...
  • Page 486 Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

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