Holtek HT32F50231 User Manual page 15

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Table 40. RTCOUT Output Mode and Active Level Setting .................................................................. 375
Table 41. RTC Register Map................................................................................................................. 376
Table 42. Watchdog Timer Register Map .............................................................................................. 385
Table 43. Conditions of Holding SCL line .............................................................................................. 404
Table 44. I 2 C Register Map ................................................................................................................... 405
Table 45. I 2 C Clock Setting Example .................................................................................................... 414
Table 46. SPI Interface Format Setup ................................................................................................... 422
Table 47. SPI Mode Fault Trigger Conditions ....................................................................................... 427
Table 48. SPI Master Mode SEL Pin Status ......................................................................................... 427
Table 49. SPI Register Map .................................................................................................................. 428
Table 50. Baud Rate Deviation Error Calculation - CK_USART = 20 MHz .......................................... 443
Table 51. Baud Rate Deviation Error Calculation - CK_USART = 10 MHz .......................................... 443
Table 52. USART Register Map ............................................................................................................ 450
Table 53. Baud Rate Deviation Error Calculation - CK_UART = 20 MHz ............................................ 467
Table 54. Baud Rate Deviation Error Calculation - CK_UART = 10 MHz ............................................ 468
Table 55. UART Register Map .............................................................................................................. 468
Table 56. DIV Register Map .................................................................................................................. 477
Table 57. CRC Register Map ................................................................................................................ 482
Rev. 1.00 15 of 486 July 31, 2018