Holtek HT32F50231 User Manual page 237

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[8] UEVIF
[7] CH3OCF
[6] CH2OCF
[5] CH1OCF
[4] CH0OCF
[3] CH3CCIF
[2] CH2CCIF
Rev. 1.00
Descriptions
Update Event Interrupt Flag
This bit is set by hardware on an update event and is cleared by software.
0: No update event occurs
1: Update event occurs
Note: The update event is derived from the following conditions:
- The counter overflows or underflows
- The UEVG bit is asserted
- A restart trigger event occurs from the slave trigger input
Channel 3 Over-Capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH3CCIF bit is already set and it is not
yet cleared by software
Channel 2 Over-Capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH2CCIF bit is already set and it is not
cleared yet by software
Channel 1 Over-Capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH1CCIF bit is already set and it is not
cleared yet by software.
Channel 0 Over-Capture Flag
This flag is set by hardware and cleared by software.
0: No over-capture event is detected
1: Capture event occurs again when the CH0CCIFbit is already set and it is not
yet cleared by software.
Channel 3 Capture / Compare Interrupt Flag
- Channel 3 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the contents of the CH3CCR
register
This flag is set by hardware when the counter value matches the CH3CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 3 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by
reading the CH3CCR register.
Channel 2 Capture / Compare Interrupt Flag
- Channel 2 is configured as an output:
0: No match event occurs
1: The contents of the counter CNTR have matched the contents of the CH2CCR
register
This flag is set by hardware when the counter value matches the CH2CCR value
except in the center-aligned mode. It is cleared by software.
- Channel 2 is configured as an input:
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by
reading the CH2CCR register.
237 of 486 July 31, 2018