Holtek HT32F50231 User Manual page 411

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[17] TXDE
[16] RXDNE
[11] TOUTF
[10] BUSERR
[9] RXNACK
[8] ARBLOS
[3] GCS
Rev. 1.00
Descriptions
Data Register Empty Using in Transmitter Mode
0: Data register I2CDR is not empty
1: Data register I2CDR is empty
This bit is set when the I2CDR register is empty in the Transmitter mode. Note that
the TXDE bit will be set after the address frame is being transmitted to inform that
the data to be transmitted should be loaded into the I2CDR register. The TXDE bit
is cleared by software writing data to the I2CDR register in both the master and
slave mode or cleared automatically by hardware after setting the STOP signal
to terminate the data transfer or setting the I2CTAR register to restart a new data
transfer in the master mode.
Data Register Not Empty in Receiver Mode
0: Data register I2CDR is empty
1: Data register I2CDR is not empty
This bit is set when the I2CDR register is not empty in the receiver mode. The
RXDNE bit is cleared by software reading the data byte from the I2CDR register.
Timeout Counter Underflow Flag
0: No timeout counter underflow occurred
1: Timeout counter underflow occurred
Writing "1" to this bit will clear the TOUTF flag.
Bus Error Flag
0: No bus error has occurred
1: Bus error has occurred
This bit is set by hardware when the I
STOP condition in a transfer process. Writing a "1" to this bit will clear the BUSERR
flag.
In Master Mode: Once the Bus Error event occurs, both the SDA and SCL lines are
released by hardware and the BUSERR flag is asserted. The application software
has to clear the BUSERR flag before the next address byte is transmitted.
In Slave Mode: Once a misplaced START or STOP condition has been detected by
the slave device, the software must clear the BUSERR flag before the next address
byte is received.
Received Not Acknowledge Flag
0: Acknowledge is returned from receiver
1: Not Acknowledge is returned from receiver
The RXNACK bit indicates that the not Acknowledge signal is received in master or
slave transmitter mode. Writing "1" to this bit will clear the RXNACK flag.
Arbitration Loss Flag
0: No arbitration loss is detected
1: Bit arbitration loss is detected
This bit is set by hardware on the current clock which the I
arbitration to another master during the address or data frame transmission. Writing
"1" to this bit will clear the ARBLOS flag. Once the ARBLOS flag is asserted by
hardware, the ARBLOS flag must be cleared before the next transmission.
General Call Slave Flag
0: No general call slave occurs
1: I 2 C interface is addressed by a general call command
When the I 2 C interface receives an address with a value of 0x00 or 0x000 in the
7-bit or 10-bit addressing mode, if both the GCEN and the AA bit are set to 1, then
it is switched as a general call slave. This flag is cleared automatically after being
read.
411 of 486
2 C interface detects a misplaced START or
2 C interface loses the bus
July 31, 2018