32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Register Map
The following table shows the RTC registers and reset values. Note all the registers in this unit are
located at the V
Table 41. RTC Register Map
Register
RTCCNT
RTCCMP
RTCCR
RTCSR
RTCIWEN
Register Descriptions
RTC Counter Register – RTCCNT
This register defines a 24-bit up-counter which is incremented by the CK_SECOND clock.
Offset:
0x000
Reset value: 0x0000_0000 (Reset by V
31
Type/Reset
23
Type/Reset
RO
0 RO
15
Type/Reset
RO
0 RO
7
Type/Reset
RO
0 RO
Bits
Field
[23:0]
RTCCNTV
Rev. 1.00
power domain.
DD15
Offset
0x000
RTC Counter Register
0x004
RTC Compare Register
0x008
RTC Control Register
0x00C
RTC Status Register
0x010
RTC Interrupt and Wakeup Enable Register
Power Domain reset only)
DD15
30
29
28
22
21
20
0 RO
0 RO
14
13
12
0 RO
0 RO
6
5
0 RO
0 RO
Descriptions
RTC Counter Value
The current value of the RTC counter is returned when reading the RTCCNT register.
The RTCCNT register is updated during the falling edge of the CK_SECOND. This
register is reset by one of the following conditions:
- Software reset – Set the PWCURST bit in the PWRCR register
- V
Power Domain power on reset – POR15
DD15
- Compare match (RTCCNT = RTCCMP) when CMPCLR = 1 (in the RTCCR
register)
- RTCEN bit changed from 0 to 1
376 of 486
Description
27
26
Reserved
19
18
RTCCNTV
0 RO
0 RO
11
10
RTCCNTV
0 RO
0 RO
4
3
2
RTCCNTV
0 RO
0 RO
Reset Value
0x0000_0000
0x0000_0000
0x0000_0F00
0x0000_0000
0x0000_0000
25
24
17
16
0 RO
0 RO
0
9
8
0 RO
0 RO
0
1
0
0 RO
0 RO
0
July 31, 2018
Need help?
Do you have a question about the HT32F50231 and is the answer not in the manual?