32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Bits
Field
[0]
NVICRSTF
AHB Peripheral Reset Register – AHBPRSTR
This register specifies several AHB peripherals software reset control bits.
Offset:
0x104
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
CRCRST
Type/Reset
RW
0
Bits
Field
[24]
DIVRST
[10]
PCRST
[9]
PBRST
[8]
PARST
[7]
CRCRST
Rev. 1.00
Descriptions
NVIC Reset Flag
0: No NVIC asserting system reset occurred
1: NVIC asserting system reset occurred
This bit is set by hardware when a system reset occurs and reset by writing 1 into it
or by hardware when a power on reset occurs.
30
29
28
22
21
20
14
13
12
Reserved
6
5
4
Descriptions
Divider Reset Control
0: No reset
1: Reset Divider
This bit is set by software and cleared to 0 by hardware automatically.
GPIO Port C Reset Control
0: No reset
1: Reset Port C
This bit is set by software and cleared to 0 by hardware automatically.
GPIO Port B Reset Control
0: No reset
1: Reset Port B
This bit is set by software and cleared to 0 by hardware automatically.
GPIO Port A Reset Control
0: No reset
1: Reset Port A
This bit is set by software and cleared to 0 by hardware automatically.
CRC Reset Control
0: No reset
1: Reset CRC
This bit is set by software and cleared to 0 by hardware automatically.
101 of 486
27
26
Reserved
19
18
Reserved
11
10
PCRST
PBRST
RW
0 RW
3
2
Reserved
25
24
DIVRST
RW
0
17
16
9
8
PARST
0 RW
0
1
0
July 31, 2018
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