Register Descriptions; Power Control Status Register - Pwrsr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

Power Control Status Register – PWRSR
This register indicates power control status.
Offset: 0x100
Reset value: 0x0000_0010
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset
Bits Field
[9] WUPF1
[8] WUPF0
[4] PORF
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
PORF
RC
Descriptions
External WAKEUP1 Pin Flag
0: The WAKEUP1 pin is not asserted
1: The WAKEUP1 pin is asserted
This bit is set by hardware when the WAKEUP1 pin asserts and is cleared by
software read. Software should read this bit to clear it after a system wake up from
the power saving mode.
External WAKEUP0 Pin Flag
0: The WAKEUP0 pin is not asserted
1: The WAKEUP0 pin is asserted
This bit is set by hardware when the WAKEUP0 pin asserts and is cleared by
software read. Software should read this bit to clear it after a system wake up from
the power saving mode.
Power On Reset Flag
0: V Power Domain reset does not occur
DD15
1: V Power Domain reset occurs
DD15
This bit is set by hardware when V
power on reset or software reset. The bit is cleared by software read. This bit must be
cleared after the system is first powered on, otherwise it will be impossible to detect
when a V Power Domain reset has been triggered. When this bit is read as 1, a
DD15
read software loop must be implemented until the bit returns again to 0.
65 of 486
27 26
Reserved
19 18
Reserved
11 10
RC
3 2
1
power on reset occurs, either a hardware
DD15
25 24
17 16
9 8
WUPF1 WUPF
0 RC 0
1 0
Reserved
July 31, 2018