Rtc Interrupt And Wakeup Enable Register - Rtciwen - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
RTC Interrupt and Wakeup Enable Register – RTCIWEN
This register contains the interrupt and wakeup enable bits.
Offset: 0x010
Reset value: 0x0000_0000 (Reset by V
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[10] OVWEN
[9] CMWEN
[8] CSECWEN
[2] OVIEN
[1] CMIEN
[0] CSECIEN
Rev. 1.00
Power Domain reset only)
DD15
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Counter Overflow Wakeup Enable
0: Counter overflow wakeup is disabled
1: Counter overflow wakeup is enabled
Compare Match Wakeup Enable
0: Compare match wakeup is disabled
1: Compare match wakeup is enabled
Counter Clock CK_SECOND Wakeup Enable
0: Counter Clock CK_SECOND wakeup is disabled
1: Counter Clock CK_SECOND wakeup is enabled
Counter Overflow Interrupt Enable
0: Counter Overflow Interrupt is disabled
1: Counter Overflow Interrupt is enabled
Compare Match Interrupt Enable
0: Compare Match Interrupt is disabled
1: Compare Match Interrupt is enabled
Counter Clock CK_SECOND Interrupt Enable
0: Counter Clock CK_SECOND Interrupt is disabled
1: Counter Clock CK_SECOND Interrupt is enabled
381 of 486
27 26
Reserved
19 18
Reserved
11 10
OVWEN CMWEN
RW 0 RW
3 2
OVIEN CMIEN
RW 0 RW
25 24
17 16
9 8
CSECWEN
0 RW 0
1 0
CSECIEN
0 RW 0
July 31, 2018