Mcu Debug Control Register - Mcudbgcr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
MCU Debug Control Register – MCUDBGCR
This register specifies debug control of MCU.
Offset: 0x304
Reset value: 0x0000_0000
31
DBPWM1 DBPWM0
Type/Reset RW 0 RW
23
Type/Reset
15
Reserved DBDSLP2
Type/Reset RW
7
Reserved DBGPTM
Type/Reset RW
Bits Field
[31] DBPWM1
[30] DBPWM0
[19] DBUR1
[18] DBUR0
[17] DBBFTM1
[16] DBBFTM0
[14] DBDSLP2
Rev. 1.00
30 29 28
0
22 21 20
Reserved
14 13 12
DBI2C1 DBI2C0
0 RW 0 RW
6 5 4
Reserved DBMCTM
0 RW
Descriptions
PWM1 Debug Mode Enable
0: PWM1 counter continues to count even if the core is halted
1: PWM1 counter is stopped when the core is halted
Set and reset by software.
PWM0 Debug Mode Enable
0: PWM0 counter continues to count even if the core is halted
1: PWM0 counter is stopped when the core is halted
Set and reset by software.
UART1 Debug Mode Enable
0: Same behavior as in normal mode
1: UART1 timeout is frozen when the core is halted
Set and reset by software.
UART0 Debug Mode Enable
0: Same behavior as in normal mode
1: UART0 timeout is frozen when the core is halted
Set and reset by software.
BFTM1 Debug Mode Enable
0: BFTM1 counter continues even if the core is halted
1: BFTM1 counter is stopped when the core is halted
Set and reset by software.
BFTM0 Debug Mode Enable
0: BFTM0 counter continues to count even if the core is halted
1: BFTM0 counter is stopped when the core is halted
Set and reset by software.
Debug Deep-Sleep2
0: LDO = Off (but turn on DMOS), FCLK = Off and HCLK = Off in Deep-Sleep2 mode
1: LDO = On, FCLK = On and HCLK = On in Deep-Sleep2 mode
Set and reset by software.
96 of 486
27 26
Reserved
19 18
DBUR1 DBUR0 DBBFTM1 DBBFTM0
RW 0 RW 0 RW
11 10
DBSPI1 DBSPI0
0 RW 0 RW 0
3 2
DBWDT Reserved
0 RW 0 RW
25 24
17 16
0 RW 0
9 8
Reserved DBUSR
RW 0
1 0
DBDSLP1 DBSLP
0 RW 0
July 31, 2018