Figure 33. Center-Aligned Counting Example - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Center-Aligned Counting
In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value
and then counts down to 0 alternatively. The Timer module generates an overflow event when the
counter counts to the counter-reload value in the up-counting mode and generates an underflow
event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in
the CNTCFR register is read-only and indicates the counting direction when in the center-aligned
mode. The counting direction is updated by hardware automatically.
Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of
whether the counter is counting up or down in the center-aligned counting mode.
The UEVIF bit in the INTSR register will be set to 1 when an overflow or underflow event or both
of them occur according to the CMSEL field setting in the CNTCFR register.
CK_PSC
CNT_EN
CK_CNT
F2
CNTR
F5
CRR
CRR Shadow
Register
Counter Overflow
Counter Underflow
Update Event Flag

Figure 33. Center-aligned Counting Example

Rev. 1.00
F3 F4 4
F5
Software clearing
Write a new value
188 of 486
3 2 1 0
4
4
1 2 3
Software clearing
July 31, 2018