Timer Counter Register - Cntr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[0] CH0CCIF
Timer Counter Register – CNTR
This register stores the timer counter value.
Offset: 0x080
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] CNTV
Rev. 1.00
Descriptions
Channel 0 Capture/Compare Interrupt Flag
- Channel 0 is configured as an output
0: No match event occurs
1: The contents of the counter CNTR have matched the content of the CH0CCR
register
This flag is set by hardware when the counter value matches the CH0CCR value
with exception in the center-aligned counting mode. It is cleared by software.
- Channel 0 is configured as an input
0: No input capture occurs
1: Input capture occurs
This bit is set by hardware on a capture event. It is cleared by software or by
reading the CH0CCR register.
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Counter Value
364 of 486
27 26
Reserved
19 18
Reserved
11 10
CNTV
0 RW 0 RW 0 RW
3 2
CNTV
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
July 31, 2018