HOLTEK HT32F12345 Manuals

Manuals and User Guides for HOLTEK HT32F12345. We have 1 HOLTEK HT32F12345 manual available for free PDF download: User Manual

HOLTEK HT32F12345 User Manual (590 pages)

32-Bit Microcontroller with Arm Cortex-M3 Core

Brand: HOLTEK | Category: Microcontrollers | Size: 6 MB

Table of Contents
2
1 Introduction

27
- Overview
  27
- Features
  28
- Device Information
  32
- Table 1. Features and Peripheral List
  32
- Block Diagram
  33
- Figure 1. Block Diagram
  33
2 Document Conventions

34
- Table 2. Document Conventions
  34
3 System Architecture

35
- Arm ® Cortex ® -M3 Processor
  35
- Bus Architecture
  36
- Figure 2. Cortex ® -M3 Block Diagram
  36
- Memory Organization
  37
  - Figure 3. Bus Architecture
    37
  - Figure 4. Memory Map
    38
  - Memory Map
    38
  - Table 3. Register Map
    39
  - AHB Peripherals
    41
  - APB Peripherals
    41
  - Embedded Flash Memory
    41
  - Embedded SRAM Memory
    41
4 Flash Memory Controller (FMC)

42
5 Power Control Unit (PWRCU)

69
6 Clock Control Unit (CKCU)

82
7 Reset Control Unit (RSTCU)

117
- Introduction
  117
- Functional Descriptions
  117
  - Power on Reset
    117
  - Figure 19. RSTCU Block Diagram
    117
  - System Reset
    118
  - AHB and APB Unit Reset
    118
- Register Map
  118
- Table 21. RSTCU Register Map
  118
- Figure 20. Power on Reset Sequence
  118
- Register Descriptions
  119
- Apbprstr0
  121
  - APB Peripheral Reset Register 1
    122
- Apbprstr1
  122
8 General Purpose I/O (GPIO)

124
9 Alternate Function Input / Output Control Unit (AFIO)

159
- Introduction
  159
- Figure 23. AFIO Block Diagram
  159
- Features
  160
- Functional Descriptions
  160
  - External Interrupt Pin Selection
    160
  - Figure 24. EXTI Channel Input Selection
    160
  - Alternate Function
    161
  - Lock Mechanism
    161
- Register Map
  161
- Table 24. AFIO Selection for Peripheral Map Example
  161
- Table 25. AFIO Register Map
  161
- Register Descriptions
  162
10 Nested Vectored Interrupt Controller (NVIC)

166
- Introduction
  166
- Table 26. Exception Types
  166
- Features
  169
- Functional Descriptions
  169
  - Systick Calibration
    169
- Register Map
  169
- Table 27. NVIC Register Map
  169
11 External Interrupt / Event Controller (EXTI)

171
12 Analog to Digital Converter (ADC)

180
13 Comparator (CMP)

215
14 General-Purpose Timer (GPTM)

224
15 Basic Function Timer (BFTM)

284
- Introduction
  284
- Features
  284
- Figure 73. BFTM Block Diagram
  284
- Functional Description
  285
  - Repetitive Mode
    285
  - Figure 74. BFTM - Repetitive Mode
    285
  - One Shot Mode
    286
  - Figure 75. BFTM - One Shot Mode
    286
  - Figure 76. BFTM - One Shot Mode Counter Updating
    286
  - Trigger ADC Start
    287
- Register Map
  287
- Table 35. BFTM Register Map
  287
- Register Descriptions
  288
16 Motor Control Timer (MCTM)

291
17 Real Time Clock (RTC)

365
- Introduction
  365
- Features
  365
- Figure 123. RTC Block Diagram
  365
- Functional Descriptions
  366
- Register Map
  368
- Table 44. RTC Register Map
  368
- Register Descriptions
  369
18 Watchdog Timer (WDT)

375
- Introduction
  375
- Features
  375
- Figure 124. Watchdog Timer Block Diagram
  375
- Functional Description
  376
- Register Map
  377
- Table 45. Watchdog Timer Register Map
  377
- Figure 125. Watchdog Timer Behavior
  377
- Register Descriptions
  378
19 Inter-Integrated Circuit

384
- 384
  384
- Introduction
  384
- Figure 126. I C Module Block Diagram
  384
- Features
  385
- Functional Descriptions
  385
  - Two Wire Serial Interface
    385
  - START and STOP Conditions
    385
  - Data Validity
    386
  - Addressing Format
    386
  - 7-Bits Address Format
    386
  - Figure 127. START and STOP Condition
    386
  - Figure 128. Data Validity
    386
  - 10-Bits Address Format
    387
  - Figure 129. 7-Bit Addressing Mode
    387
  - Figure 130. 10-Bit Addressing Write Transmit Mode
    387
  - Data Transfer and Acknowledge
    388
  - Figure 131. 10-Bits Addressing Read Receive Mode
    388
  - Figure 132. I C Bus Acknowledge
    388
  - Clock Synchronization
    389
  - Arbitration
    389
  - Figure 133. Clock Synchronization During Arbitration
    389
  - Figure 134. Two Master Arbitration Procedure
    389
  - General Call Address
    390
  - Bus Error
    390
  - Address Mask Enable
    390
  - Address Snoop
    390
  - Operation Mode
    390
  - Figure 135. Master Transmitter Timing Diagram
    391
  - Figure 136. Master Receiver Timing Diagram
    393
  - Figure 137. Slave Transmitter Timing Diagram
    394
  - Conditions of Holding SCL Line
    395
  - Table 46. Conditions of Holding SCL Line
    395
  - Figure 138. Slave Receiver Timing Diagram
    395
  - I 2 C Timeout Function
    396
  - PDMA Interface
    396
- Register Map
  397
- Table 47. I 2 C Register Map
  397
- Register Descriptions
  398
20 Serial Peripheral Interface (SPI)

411
21 Universal Synchronous Asynchronous Receiver Transmitter (USART)

431
- Introduction
  431
- Figure 150. USART Block Diagram
  431
- Features
  432
- Functional Descriptions
  432
- Register Map
  441
- Table 55. USART Register Map
  441
- Register Descriptions
  442
22 Universal Asynchronous Receiver Transmitter (UART)

455
- Introduction
  455
- Figure 161. UART Block Diagram
  455
- Features
  456
- Functional Descriptions
  456
- Register Map
  459
- Table 58. UART Register Map
  459
- Register Descriptions
  460
23 USB Device Controller (USB)

467
24 Peripheral Direct Memory Access (PDMA)

496
- Introduction
  496
- Features
  496
- Figure 167. PDMA Block Diagram
  496
- Functional Description
  497
  - AHB Master
    497
  - PDMA Channel
    497
  - PDMA Request Mapping
    497
  - Figure 168. PDMA Request Mapping Architecture
    497
  - Channel Transfer
    498
  - Channel Priority
    498
  - Table 63. PDMA Channel Assignments
    498
  - Transfer Request
    499
  - Address Mode
    499
  - Table 64. PDMA Address Modes
    499
  - Figure 169. PDMA Channel Arbitration and Scheduling Example
    499
  - Auto-Reload
    500
  - Transfer Interrupt
    500
- Register Map
  500
- Table 65. PDMA Register Map
  500
- Register Descriptions
  503
25 Extend Bus Interface (EBI)

514
26 Inter-IC Sound

539
27 Cyclic Redundancy Check (CRC)

559
- Introduction
  559
- Features
  559
- Figure 206. CRC Block Diagram
  559
- Functional Descriptions
  560
  - CRC Computation
    560
  - Byte and Bit Reversal for CRC Computation
    560
  - Figure 207. CRC Data Bit and Byte Reversal Example
    560
  - CRC with PDMA
    561
- Register Map
  561
- Table 74. Register Map of CRC
  561
- Register Descriptions
  562
  - CRC Control Register - CRCCR
    562
  - CRC Seed Register - CRCSDR
    563
  - CRC Checksum Register - CRCCSR
    563
  - CRC Data Register - CRCDR
    564
28 SDIO Host Controller (SDIO)

565
- Introduction
  565
- Features
  565
- Functional Description
  565
  - Figure 208. SDIO Bus Topology
    565
  - Figure 209. SDIO Block Diagram
    565
  - Figure 210. Normal Speed Timing
    566
  - Figure 211. High Speed Timing
    566
  - Figure 212. SD_CLK Duty Cycle
    566
  - SD Clock
    566
  - Figure 213. "No Response" and "No Data" Operations
    567
  - Figure 214. "Multiple" Block Read Operation
    567
  - Figure 215. "Multiple" Block Write Operation
    567
  - SD Protocol
    567
  - Command
    568
  - Figure 216. Command Format
    568
  - Figure 217. Response Format
    568
  - Response
    568
  - Table 75. Command Format
    568
  - Table 76. Response R1 Format
    568
  - Data
    569
  - Figure 218. Usual Data Format for Standard Bus - Only DAT0 Used
    569
  - Table 77. Response R2 Format
    569
  - Table 78. Response R3 Format
    569
  - Table 79. Response R6 Format
    569
  - Figure 219. Usual Data Format for Wide Bus - DAT0~DAT3 Used
    570
  - Figure 220. Wide Width Data Format for Standard Bus - Only DAT0 Used
    570
  - Figure 221. Wide Width Data Format for Wide Bus - DAT0 ~ DAT3 Used
    570
  - Buffer Status
    571
  - DMA Request
    571
  - Interrupt
    571
- Register Map
  572
- Register Description
  573
  - Block Size Register - BLSIZE
    573
  - Block Count Register - BLCNT
    574
  - Argument Register - ARG
    574
  - Transfer Mode Register - TMR
    575
  - Command Register - CMD
    576
- Response Register N - Respn, N = 0 ~ 3
  577
- Data Port Register - DR
  578
- Present State Register - PSR
  578
- Control Register - CR
  580
- Clock Control Register - CLKCR
  581
- Timeout Control Register - TMOCR
  582
- Software Reset Register - SWRST
  583
- Status Register - SR
  584
- Status Enable Register - SER
  586
- Interrupt Enable Register - IER
  588

HOLTEK Categories

Microcontrollers

Storage Computer Hardware Control Unit Motherboard

More HOLTEK Manuals

HOLTEK HT32F12345 Manuals

HOLTEK HT32F12345 User Manual (590 pages)

Table of Contents

1 Introduction

2 Document Conventions

3 System Architecture

4 Flash Memory Controller (FMC)

5 Power Control Unit (PWRCU)

6 Clock Control Unit (CKCU)

7 Reset Control Unit (RSTCU)

8 General Purpose I/O (GPIO)

9 Alternate Function Input / Output Control Unit (AFIO)

10 Nested Vectored Interrupt Controller (NVIC)

11 External Interrupt / Event Controller (EXTI)

12 Analog to Digital Converter (ADC)

13 Comparator (CMP)

14 General-Purpose Timer (GPTM)

15 Basic Function Timer (BFTM)

16 Motor Control Timer (MCTM)

17 Real Time Clock (RTC)

18 Watchdog Timer (WDT)

19 Inter-Integrated Circuit

20 Serial Peripheral Interface (SPI)

21 Universal Synchronous Asynchronous Receiver Transmitter (USART)

22 Universal Asynchronous Receiver Transmitter (UART)

23 USB Device Controller (USB)

24 Peripheral Direct Memory Access (PDMA)

25 Extend Bus Interface (EBI)

26 Inter-IC Sound

27 Cyclic Redundancy Check (CRC)

28 SDIO Host Controller (SDIO)

Related Products

HOLTEK Categories