Watchdog Timer Mode Register 0 - Wdtmr0 - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Watchdog Timer Mode Register 0 – WDTMR0
This register specifies the Watchdog timer counter reload value and reset enable control.
Offset: 0x004
Reset value: 0x0000_0FFF
31
Type/Reset
23
Type/Reset
15
WDTSHLT WDTRSTEN Reserved
Type/Reset RW 0 RW
7
Type/Reset RW 1 RW
Bits Field
[16] WDTEN
[15:14] WDTSHLT
[13] WDTRSTEN
[11:0] WDTV
Rev. 1.00
30 29
22 21
14 13
0 RW 0
6 5
1 RW 1 RW
Descriptions
Watchdog Timer Running Enable
0: Watchdog timer is disabled
1: Watchdog timer is enabled to run
When the Watchdog timer is disabled, the counter will be reset to its hardware
default condition. When the WDTEN bit is set, the Watchdog timer will be reloaded
with the WDTV value and count down.
Watchdog Timer Sleep Halt
00: The Watchdog runs when the system is in the Sleep mode or Deep-Sleep1
mode
01: The Watchdog runs when the system is in the Sleep mode and halts in Deep-
Sleep1 mode
10 or 11: The Watchdog halts when the system is in the Sleep mode and Deep-
Sleep1 mode
Note that the Watchdog timer always halts when the system is in Deep-Sleep2 mode.
The Watchdog stops counting when the WDTSHLT bits are properly configured in the
Sleep mode or Deep-Sleep1 mode, the count value is retained so that it continues
counting after the system wakes up from these three Sleep modes. If a Watchdog
reset occurs in Sleep mode or Deep-Sleep1 mode, it will wake up the device.
Watchdog Timer Reset Enable
0: A Watchdog Timer underflow or error has no effect on the reset of system
1: A Watchdog Timer underflow or error triggers a Watchdog timer system reset
Watchdog Timer Counter Value
WDTV defines the value loaded into the 12-bit Watchdog down-counter.
386 of 486
28 27 26
Reserved
20 19 18
Reserved
12 11 10
RW 1 RW
4 3 2
WDTV
1 RW 1 RW
25 24
17 16
WDTEN
RW 0
9 8
WDTV
1 RW 1 RW 1
1 0
1 RW 1 RW 1
July 31, 2018