32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Channel Controller
The MCTM has four independent channels which can be used as capture inputs or compare match
outputs. Each capture input or compare match output channel is composed of a preload register
and a shadow register. Data access of the APB bus is always implemented by reading/writing the
preload register.
When used in the input capture mode, the counter value is captured into the CHxCCR shadow
register first and then transferred into the CHxCCR preload register when the capture event occurs.
When used in the compare match output mode, the contents of the CHxCCR preload register is copied
into the associated shadow register, the counter value is then compared with the register value.
CHxPSC
Capture
Controller
Read CHxCCR
CHxCCS
CHxCCG
CHxE
Figure 106. Capture/Compare Block Diagram
Capture Counter Value Transferred to CHxCCR
When the channel is used as a capture input, the counter value is captured into the Channel
Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the
capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly. If the CHxCCIF
bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on
this channel occurs, the corresponding channel Over-Capture flag, named CHxOCF, will be set.
MT_CH0
(TI0)
25
CNTR
CHxCCR
0
CHxCCIF
CHxOCF
Figure 107. Input Capture Mode
Rev. 1.00
APB Bus Interface
CHxCCR
(Preload Register)
Capture Transfer
CHxCCR
(Shadow Register)
Capture
26
27
28
29
26
308 of 486
Compare
Compare Transfer
Controller
CHxCCS
CHxPRE
CHxCCR
TM_CNT
30
31
32
33
Write CHxCCR
Update Event 1
34
35
32
July 31, 2018
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