32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Word Programming
The FMC provides a 32 bits word programming function which is used for modifying the Flash
memory content. The following steps show the sequence of register access for word programming.
▄
Check OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been finished.
▄
Write word address to TADR register. Write data to WRDR register.
▄
Write word program command to OCMR register (Set CMD [3:0] = 0x4).
▄
Commit word program command to FMC by setting OPCR register (Set OPM [3:0] = 0xA).
▄
Wait until all operations have been finished by checking the value of OPCR register (OPM [3:0]
equals to 0xE).
▄
Read and verify the Flash memory if required.
Note that the word programming operation can not be successively applied to the same address
twice. Successive word programming operation to the same address must be separated by a page
erase operation. Besides, the word program will be ignored on protected pages. When this occurs,
the OREF bit will be set by the FMC and then a Flash Operation Error interrupt will be generated if
the OREIEN bit in the OIER register is set. Software can check the PPEF bit in the OISR register to
detect this condition in the interrupt handler. The following figure displays the word programming
operation flow.
Figure 10. Word Programming Operation Flowchart
Rev. 1.00
Start
No
Is OPM equal to 0xE or 0x6 ?
Yes
Set TADR, WRDR
and OCMR
Commit command
by setting OPCR
No
Is OPM equal to 0xE ?
Yes
Finish
40 of 486
July 31, 2018
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