Register Descriptions; Usart Data Register - Usrdr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

USART Data Register – USRDR
The register is used to access the USART transmitted and received FIFO data.
Offset: 0x000
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset RW 0 RW
Bits Field
[8:0] DB
Rev. 1.00
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
0 RW 0 RW
Descriptions
Reading data via this receiver buffer register will return the data from the receive
FIFO. The receive FIFO has a capacity of up to 8 × 9 bits. By reading this register,
the USART will return a 7, 8 and 9-bit received data. The DB field bit 8 is valid for
9-bit mode only and is fixed at 0 for the 8-bit mode. For the 7-bits mode, the DB[6:0]
field contains the available bits.
Writing data to this buffer register will load data into the Transmit FIFO. The Transmit
FIFO has a capacity of up to 8 × 9 bits. By writing to this register, the USART will
send out 7, 8 or 9-bit transmitted data. The DB field bit 8 is valid for the 9-bit mode
only and will be ignored for the 8-bit mode. For the 7-bit mode, the DB[6:0] field
contains the available bits.
451 of 486
27 26
Reserved
19 18
Reserved
11 10
3 2
DB
0 RW 0 RW 0 RW
25 24
17 16
9 8
DB
RW 0
1 0
0 RW 0
July 31, 2018