Figure 129. Immediate Active Mode Minimum Delay - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.
However, there exist several clock delays to perform the comparison result between the counter
value and the CHxCCR value. In order to reduce the delay to a minimum value, users can set the
CHxIMAE bit in each CHxOCFR register. After an STI rising edge trigger occurs in the single
pulse mode, the CHxOREF signal will immediately be forced to the state to which the CHxOREF
signal will change to as the compare match event occurs without taking the comparison result into
account. The CHxIMAE bit is available only when the output channel is configured to operate in
the PWM mode 1 or PWM mode 2 and the trigger source is derived from the STI signal.
Counter Value
CKDIV = 0
CRR
CHxCCR
CK_CNT
ITIx
STI
TME
CHxIMAE
CHxOREF
(PWM1)
(PWM2)

Figure 129. Immediate Active Mode Minimum Delay

Rev. 1.00
Up-Counting Mode
1
0
Counter Start Time
Minimum delay
325 of 486
6
5
4
3
2
Time
July 31, 2018