Uart Interrupt Enable Register - Urier - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[5] URRXEN
[4] URTXEN
[2] TRSM
UART Interrupt Enable Register – URIER
This register is used to enable the related UART interrupt function. The UART module generates interrupts to the
controller when the corresponding events occur and the corresponding interrupt enable bits are set.
Offset: 0x00C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved
Type/Reset RW
Bits Field
[6] BIE
[5] FEIE
[4] PEIE
Rev. 1.00
Descriptions
UART RX Enable
0: Disable
1: Enable
UART TX Enable
0: Disable
1: Enable
Transfer Mode Selection
This bit is used to select the data transfer protocol.
0: LSB first
1: MSB first
30 29 28
22 21 20
14 13 12
6 5 4
BIE FEIE PEIE
0 RW 0 RW
Descriptions
Break Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt is generated when the break interrupt is enabled and
the BII bit is set in the URSIFR register.
Framing Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt is generated when the framing error interrupt is
enabled and the FEI bit is set in the URSIFR register.
Parity Error Interrupt Enable
0: Disable interrupt
1: Enable interrupt
If this bit is set, an interrupt is generated when the parity error interrupt is enabled
and the PEI bit is set in the URSIFR register.
471 of 486
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
OEIE TXCIE
0 RW 0 RW 0 RW
25 24
17 16
9 8
1 0
TXDEIE RXDRIE
0 RW 0
July 31, 2018