Pad Assignment
1
4 4
P B 3
2
P B 2
3
4
P B 1
5
P B 0
V S S
6
7
P E 0
8
P E 1
9
P E 2
P E 3
1 0
I N T
1 1
1 2
T M R
1 3 1 4 1 5
* The IC substrate should be connected to VSS in the PCB layout artwork.
* The TMR pad must be bound to VDD or VSS if it is not used.
4 3
4 2
4 0
3 9
3 8
4 1
( 0 , 0 )
1 8 1 9
1 6
1 7
2 0
2 1
2 2 2 3
2 4
Chip size: 3555 ´ 5015 (mm)
3
3 7
3 6
3 5
3 4
3 3
O S C 2
3 2
O S C 1
3 1
V D D
3 0
R E S
2 9
A U D
2 5
2 6
2 7
2 8
2
March 15, 2000
HT827A0
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