32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F50231/HT32F50241
Repetition Down-counter Operation
The update event 1 is usually generated at each overflow or underflow event occurrence. However,
when the repetition operation is active by assigning a non-zero value into the REPR register, the
update event is only generated if the REPR counter has reached zero. The REPR value is decreased
when the following conditions occur:
▄
At each counter overflow in the up-counting mode
▄
At each counter underflow in the down-counting mode
▄
At each counter overflow and underflow in the center-aligned counting mode
CK_CNT
Up-Counting
CNTR
0
1
2
REPR
REPR Counter = 0
UEV1
Down-Counting
CNTR
3
2
1
REPR
REPR Counter = 0
UEV1
Center-Aligned-Counting
CK_CNT
CNTR
2
3
4
3
2
REPR
REPR Counter = 1
UEV1
Figure 97. Update Event 1 Dependent Repetition Mechanism Example
Rev. 1.00
3
4
5
0
1
REPR Counter = 1
0
3
2
1
0
REPR Counter = 2
1
0
1
2
3
4
REPR Counter = 0
REPR Counter = 1
302 of 486
2
3
4
5
0
1
3
2
1
0
3
2
REPR Counter = 1
3
2
1
0
1
2
3
1
REPR Counter = 1 REPR Counter = 0
REPR Counter = 0
1
2
3
4
REPR Counter = 0
2
1
0
3
REPR Counter = 0
4
3
2
1
0
July 31, 2018
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