Figure 65. Down-Counting Example - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Down-Counting
In this mode the counter counts continuously from the counter reload value, which is defined in
the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module
generates an underflow event and the counter restarts to count once again from the counter reload
value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 1 for the down-counting mode.
When the update event is set by the UEVG bit in the EVGR register, the counter value will also be
initialized to the counter reload value.
CK_PSC
CNT_EN
CK_CNT
CNTR 3
CRR F5
CRR Shadow
Register
PSCR
PSCR Shadow
Register
PSC_CNT
Counter Underflow
Update Event Flag
Write a new value

Figure 65. Down-counting Example

Rev. 1.00
2 1 0
F5
0
0
0
Update a new value
249 of 486
36 35
36
36
1
1
0 1 0 1 0
Software clearing
34 33
1 0 1
July 31, 2018