Channel 0 Output Configuration Register - Ch0Ocfr - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[17:16] CH3CCS
[3:0] TI3F
Channel 0 Output Configuration Register – CH0OCFR
This register specifies the channel 0 output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Reserved CH0IMAE
Type/Reset
Rev. 1.00
Descriptions
Channel 3 Capture / Compare Selection
00: Channel 3 is configured as an output
01: Channel 3 is configured as an input derived from the TI3 signal
10: Channel 3 is configured as an input derived from the TI2 signal
11: Channel 3 is configured as an input which comes from the TRCED signal
derived from the Trigger Controller
Note: The CH3CCS field can be accessed only when the CH3E bit is cleared to 0
Channel 3 Input Source TI3 Filter Setting
These bits define the frequency divided ratio used to sample the TI3 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many
valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
0001: f = f , N = 2
SAMPLING CLKIN
0010: f = f , N = 4
SAMPLING CLKIN
0011: f = f , N = 8
SAMPLING CLKIN
0100: f = f / 2, N = 6
SAMPLING DTS
0101: f = f / 2, N = 8
SAMPLING DTS
0110: f = f / 4, N = 6
SAMPLING DTS
0111: f = f / 4, N = 8
SAMPLING DTS
1000: f = f / 8, N = 6
SAMPLING DTS
1001: f = f / 8, N = 8
SAMPLING DTS
1010: f = f / 16, N = 5
SAMPLING DTS
1011: f = f / 16, N = 6
SAMPLING DTS
1100: f = f / 16, N = 8
SAMPLING DTS
1101: f = f / 32, N = 5
SAMPLING DTS
1110: f = f / 32, N = 6
SAMPLING DTS
1111: f = f / 32, N = 8
SAMPLING DTS
30 29 28
22 21 20
14 13 12
6 5 4
CH0PRE
RW 0 RW
224 of 486
SYSTEM
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
Reserved CH0OM[2:0]
0 RW 0 RW
25 24
17 16
9 8
CH0OM[3]
RW 0
1 0
0 RW 0
July 31, 2018