Features - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Interrupt Exception Exception
Number Number
14 30 Reserved
15 31 PWM0
16 32 PWM1
17 33 BFTM0
18 34 BFTM1
19 35 I 2 C0
20 36 I 2 C1
21 37 SPI0
22 38 SPI1
23 39 USART
24 40 Reserved
25 41 UART0
26 42 UART1
27 43 Reserved
28 44 Reserved
29 45 Reserved
30 46 Reserved
31 47 Reserved
Notes: 1. The exception priority can be changed using the NVIC System Handler Priority Registers. For more
information, refer to the Arm
2. The interrupt priority can be changed using the NVIC Interrupt Priority Registers. For more information,
refer to the Arm ® "Cortex

Features

▄
7 system Cortex
▄
Up to 32 Maskable peripheral interrupts
▄
4 programmable priority levels (2 bits for interrupt priority setting)
▄
Non-Maskable interrupt
▄
Low-latency exception and interrupt handling
▄
Vector table remapping capability
● Integrated simple, 24-bit system timer, SysTick
● 24-bit down-counter
● Auto-reloading capability
● Maskable system interrupt generation when counter decreases to 0
● SysTick clock source derived from the HCLK clock divided by 8
Rev. 1.00
Priority
Type
—
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
Configurable (2)
—
Configurable (2)
Configurable (2)
—
—
—
—
—
"Cortex -M0+ Devices Generic User Guide" document.
® ®
® -M0+ Devices Generic User Guide" document.
-M0+ exceptions
®
147 of 486
Vector
Description
Address
0x078
0x07C PWM0 global interrupt
0x080 PWM1 global interrupt
0x084 BFTM0 global interrupt
0x088 BFTM1 global interrupt
0x08C I 2 C0 global interrupt
0x090 I 2 C1 global interrupt
0x094 SPI0 global interrupt
0x098 SPI1 global interrupt
0x09C USART global interrupt
0x0A0
0x0A4 UART0 global interrupt
0x0A8 UART1 global interrupt
0x0AC
0x0B0
0x0B4
0x0B8
0x0BC
—
—
—
—
—
—
—
July 31, 2018