Figure 109. Channel 0 And Channel 1 Input Stages; Figure 110. Channel 2 And Channel 3 Input Stages - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
TI0SRC
MT_CH0
TI0XOR
MT_CH1
XOR
MT_CH2
TI0
TI0FP
Filter
f
sampling
TI0F
TI1
TI1FP
MT_CH1
Filter
f
sampling
TI1F

Figure 109. Channel 0 and Channel 1 Input Stages

TI2
MT_CH2
Filter
f
sampling
TI2F
TI3
MT_CH3
Filter
f
sampling
TI3F

Figure 110. Channel 2 and Channel 3 Input Stages

Digital Filter
The digital filters are embedded in the input stage and clock controller block for the MT_CH0 ~
MT_CH3 pins. The digital filter in the MCTM is an N-event counter where N refers to how many
valid transitions are necessary to output a filtered signal. The N value can be 0, 2, 4, 5, 6 or 8
according to the selection for each filter.
Rev. 1.00
TRCED
f
Edge
CLKIN
Detection
Edge
Detection
f
CLKIN
TI0S0
TI0FN
CH0P
TI1S0
TI0S1
CH1P
TI1S1
TI1FN
TRCED
f
CLKIN
TI2FP
TI2S2
TI2FN
CH2P
TI3S2
TI2S3
CH3P
TI3FP
TI3S3
TI3FN
310 of 486
CH0CCS
Edge
TI0S0ED
Detection
CH0PRESCALER
Edge
TI1S0ED
Detection
Edge
TI0S1ED
Detection
CH1PRESCALER
Edge
TI1S1ED
Detection
CH1CCS
CH2CCS
Edge TI2S2ED
Detection
CH2PRESCALER
Edge TI3S2ED
Detection
Edge
TI2S3ED
Detection
CH3PRESCALER
Edge
TI3S3ED
Detection
CH3CCS
TI0BED
CH0PSC
CH0CAP Event
CH0PSC
CH1PSC
CH1CAP Event
CH1PSC
CH2PSC
CH2CAP Event
CH2PSC
CH3PSC
CH3CAP Event
CH3PSC
July 31, 2018