Holtek HT32F50231 User Manual page 231

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
Bits Field
[8][2:0] CH3OM[3:0] Channel 3 Output Mode Setting
Rev. 1.00
Descriptions
These bits define the functional types of the output reference signal CH3OREF
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH3OREF is forced to 0
0101: Force active – CH3OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 3 has an active level when CNTR <
CH3CCR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CCR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3CCR or otherwise has an inactive level
1110: Asymmetric PWM mode 1
- During up-counting, channel 3 has an active level when CNTR <
CH3CCR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CCR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3ACR or otherwise has an inactive level
Note: When channel 3 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Center-
aligned Counting mode (CMSEL = 0x1 / 0x2 / 0x3)
231 of 486 July 31, 2018