Apb Clock Control Register 0 - Apbccr0 - Holtek HT32F50231 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
APB Clock Control Register 0 – APBCCR0
This register specifies clock enable bits of APB peripherals.
Offset: 0x02C
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
EXTIEN
Type/Reset RW 0 RW
7
Reserved
Type/Reset
Bits Field
[15] EXTIEN
[14] AFIOEN
[11] UR1EN
[10] UR0EN
[8] USREN
[5] SPI1EN
[4] SPI0EN
Rev. 1.00
30 29 28
22 21 20
14 13 12
AFIOEN Reserved
0
6 5
SPI1EN SPI0EN
RW 0 RW
Descriptions
External Interrupt Clock Enable
0: EXTI clock is disabled
1: EXTI clock is enabled
Set and reset by software.
Alternate Function I/O Clock Enable
0: AFIO clock is disabled
1: AFIO clock is enabled
Set and reset by software.
UART1 Clock Enable
0: UART1 clock is disabled
1: UART1 clock is enabled
Set and reset by software.
UART0 Clock Enable
0: UART0 clock is disabled
1: UART0 clock is enabled
Set and reset by software.
USART Clock Enable
0: USART clock is disabled
1: USART clock is enabled
Set and reset by software.
SPI1 Clock Enable
0: SPI1 clock is disabled
1: SPI1 clock is enabled
Set and reset by software.
SPI0 Clock Enable
0: SPI0 clock is disabled
1: SPI0 clock is enabled
Set and reset by software.
86 of 486
27 26
Reserved
19 18
Reserved
11 10
UR1EN UR0EN
RW 0 RW
4 3 2
Reserved
0
25 24
17 16
9 8
Reserved USREN
0 RW 0
1 0
I2C1EN I2C0EN
RW 0 RW 0
July 31, 2018