Holtek HT32F50231 User Manual page 13

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F50231/HT32F50241
22 Universal Asynchronous Receiver Transmitter (UART) ................................ 465
Introduction ........................................................................................................................ 465
Features ............................................................................................................................. 466
Function Descriptions ........................................................................................................ 466
Serial Data Format ........................................................................................................................ 466
Baud Rate Generation .................................................................................................................. 467
Interrupts and Status .................................................................................................................... 468
Register Map ..................................................................................................................... 468
Register Descriptions ......................................................................................................... 469
UART Data Register - URDR ....................................................................................................... 469
UART Control Register - URCR ................................................................................................... 470
UART Interrupt Enable Register - URIER .................................................................................... 471
UART Status & Interrupt Flag Register - URSIFR ....................................................................... 472
UART Divider Latch Register - URDLR ....................................................................................... 474
UART Test Register - URTSTR .................................................................................................... 475
23 Divider (DIV) ...................................................................................................... 476
Introduction ........................................................................................................................ 476
Features ............................................................................................................................. 476
Functional Descriptions ..................................................................................................... 476
Register Map ..................................................................................................................... 477
Register Descriptions ......................................................................................................... 477
Divider Control Register - CR ...................................................................................................... 477
Dividend Data Register - DDR ..................................................................................................... 478
Divisor Data Register - DSR ........................................................................................................ 478
Quotient Data Register - QTR ...................................................................................................... 479
Remainder Data Register - RMR ................................................................................................. 479
24 Cyclic Redundancy Check (CRC) .................................................................... 480
Introduction ....................................................................................................................... 480
Features ............................................................................................................................. 480
Functional Descriptions ..................................................................................................... 481
CRC Computation ......................................................................................................................... 481
Byte and Bit Reversal for CRC Computation ................................................................................ 481
Register Map ..................................................................................................................... 482
Register Descriptions ......................................................................................................... 482
CRC Control Register - CRCCR .................................................................................................. 482
CRC Seed Register - CRCSDR ................................................................................................... 483
CRC Checksum Register - CRCCSR .......................................................................................... 484
CRC Data Register - CRCDR ...................................................................................................... 485
Rev. 1.00 13 of 486 July 31, 2018